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Author SHA1 Message Date
Simon Zeni 90be0d7963 glapi/gl_gentable.py: drop call to backtrace on no op 
The function uses glibc specific functions

Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12108>
 2021-08-26 01:47:30 +00:00
Simon Zeni 0bbb9001c2 i915: remove use of backtrace and backtrace_symbols 
The function `debug_backtrace` relied on glibc specific functions, and is
unused unless someone manually patches the source to set DEBUG_BACKTRACE_SIZE

Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12108>
 2021-08-26 01:47:30 +00:00
Nanley Chery 565f9105b7 anv/image: Don't assert that HiZ can be added 
HiZ isn't yet enabled for Tile4/64.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 0022a11ff4 iris: Disable tiled memcpy for Tile4 
ISL's tiled memcpy functions don't support it yet.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Jordan Justen fd509ef59d iris: Disable the Y-tiled modifiers on XeHP+ 
I915_FORMAT_MOD_Y_TILED_CCS was already disabled for Xe+ due to a change
in the CCS layout. Disable the remaining Y-tiled modifiers since XeHP
lacks support for Y-tiling.

Rework:
* Nanley: Include Anuj's fix for the non-CCS modifiers.
* Nanley: Split out Anuj's fix into a separate if statement.
* Nanley: Rewrite commit message.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery bd516c6581 intel/isl: Disable I915_FORMAT_MOD_Y_TILED on XeHP+ 
XeHP lacks support for Y-tiling.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery af40104e7d intel: Add underscores to HALIGN and VALIGN enums 
The HALIGN enums for XeHP already have underscores. Make the other
HALIGN and VALIGN enums conform.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 3d1f6342c0 intel: Update surface states for XeHP alignments 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery fbde743b07 intel/isl: Use a switch for HALIGN/VALIGN encoding 
Avoid using a sparse and relatively large array for HALIGN encoding.
Additionally, this provides validation of the input alignment values.

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 2e464e69b9 intel/isl: Fix halign/valign of uncompressed views 
We're going to start asserting for valid halign/valign values during
surface state emission. Pre-SKL, isl_surf_get_uncompressed_surf creates
uncompressed surfaces with invalid halign/valign values - 1x1. Fix this
by replacing the call to isl_surf_get_image_surf with isl_surf_init,
passing in the uncompressed format up-front.

As we're no longer using isl_surf_get_image_surf, we also need to get
the x and y offset of the image ourselves. Instead of getting a
sample-based offset, then converting to elements later on, we use
isl_surf_get_image_offset_B_tile_el to get the offset in elements
up-front.

With the above two changes, the generic code after the else-block is no
longer needed for the single-layer-view code path. We move it and
specialize it to the if-block (which is executed SKL+ and handles
multi-layer views).

Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery c7bcbc950c intel/blorp: Fix Gfx7 stencil surface state valign 
Stencil on Gfx7 has a vertical alignment element of 8, but the largest
its surface state can express is 4. Apply the Gfx6 solution of changing
the alignment in blorp_surf_retile_w_to_y.

Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 1f62cddaf5 intel/blorp: Fix faked RGB image alignment on XeHP 
On XeHP, NPOT and POT formatted surfaces will use different image
alignment units when emitting surface states. When BLORP fakes an RGB
image as RED, update the image alignment to prevent assert failures when
emitting surface states.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 79ad9cda48 intel: Support Tile4/64 in surface states 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery dd9ae2dc7b intel: Support Tile4/64 in depth/stencil state 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery f54de77c3a intel/isl: Update tiling filter functions for XeHP 
Enable the XeHP-specific tilings and restrict them to that platform.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 0ab2fa18e4 intel/isl: Use an allow-list in gfx6_filter_tiling 
Try to avoid having to update isl_gfx6_filter_tiling when new tilings
are added for new platforms. Note that the allow-list uses
ISL_TILING_ANY_Y_MASK and thus assumes that no new Y-tilings will be
added in the future.

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 602f597bc1 intel/isl: Drop ISL_SURF_USAGE_DISPLAY_*_BIT 
We haven't used these since their introduction.

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery ac37d7801c intel/isl: Drop extra assert on array_pitch_el_rows 
ISL already asserts that the variable is a multiple of the tile height
via isl_assert_div.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 4309012774 intel/isl: Size Tile64 surfaces with 4 dimensions 
In order to size Tile64 surfaces correctly, make sure that the total
physical extent is arrayed. The code should handle 3D surfaces as well,
but is untested for now.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 8fd7678241 intel/isl: Update image alignments on XeHP 
Implement the new XeHP alignment rules for surface layout.
RENDER_SURFACE_STATE objects still need updating, but that's left for a
separate commit.

Rework:
* Nanley: Include Sagar's VALIGN fix for D16_UNORM.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 0bcfa2d8fb intel/isl: Define ISL_TILING_4/64 for XeHP 
XeHP defines new tiling formats, Tile4 and Tile64. They are needed in
order to support depth/stencil surfaces and multisampling. Create new
ISL enums and define some initial tiling information in order to enable
them later on.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 44ef425ce8 intel/isl: Add msaa_layout param to isl_tiling_get_info 
The additional parameter will be used by Tile64.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Jason Ekstrand e307d46eab intel/isl: Add more parameters to isl_tiling_get_info 
They are not used yet but the layout of Yf and Ys tiles are dependent on
these parameters.  While we're here, better document the function.

Rework:
* Nanley: Update crocus.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Mike Blumenkrantz 5200a99062 zink: only remove programs from hash tables on shader deletion if needed 
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
 2021-08-25 17:29:10 -04:00
Mike Blumenkrantz c12a985894 zink: set inlinable_uniforms_mask first when binding a shader 
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
 2021-08-25 17:29:10 -04:00
Mike Blumenkrantz ec814f7d36 zink: add some null checks for shader variant key generation 
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
 2021-08-25 17:29:10 -04:00
Mike Blumenkrantz e7b0541d45 zink: stop using dirty_shader_stages for shader binds 
by only using this mask for variant updates, we can begin to do some
neat things

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
 2021-08-25 17:29:10 -04:00
Mike Blumenkrantz 191ae5193c zink: simplify a bitmask init 
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
 2021-08-25 17:29:10 -04:00
Mike Blumenkrantz 5f3cb4c490 zink: create compute programs on bind 
this simplifies the launch_grid codepath and gets shader binds out
the shader update bitmask

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
 2021-08-25 17:29:10 -04:00
Mike Blumenkrantz e14ecb903b zink: avoid hashing shader stages multiple times for new gfx programs 
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
 2021-08-25 17:29:10 -04:00
Mike Blumenkrantz 4b5e26e678 zink: split gfx shader cache based on stages present 
this makes the pool of progs in a given hash smaller and also minimizes
the hashing required for a given program

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
 2021-08-25 17:29:08 -04:00
Mike Blumenkrantz 2d54e8da50 zink: track mask of bound gfx shader stages 
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
 2021-08-25 17:27:45 -04:00
Mike Blumenkrantz ad6847cf53 zink: inline program cache structs 
derefs--

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
 2021-08-25 17:27:45 -04:00
Mike Blumenkrantz bdbcf256a1 zink: return early when getting resource modifer if no modifier is used 
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12534>
 2021-08-25 21:14:11 +00:00
Mike Blumenkrantz 325fbc3fd2 zink: verify program key sizes before checking for default variant 
currently keys for shaders are always the same size, but this will change
in the future, at which point the keysize becomes relevant

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12547>
 2021-08-25 21:01:27 +00:00
Michael Tang 4a3395f35a microsoft/compiler: Miscellaneous fixes from running clang-format 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12513>
 2021-08-25 20:19:05 +00:00
Michael Tang 1aca20be14 microsoft/compiler: Emit a flat interpolation method for SV_SampleIndex 
We do not want to set an interpolation method for vertex shader inputs.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12513>
 2021-08-25 20:19:05 +00:00
Michael Tang 74a24f4f1c microsoft/compiler: Set the SampleFrequency runtime metadata 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12513>
 2021-08-25 20:19:05 +00:00
Michael Tang 88220083cf microsoft/compiler: More robustly handle setting Register=-1 
This is the 'N/A mask' case in the DXIL disassembly.

This logic is taken from: https://github.com/microsoft/DirectXShaderCompiler/blob/7c9e487afd17b7726229d8ceb3242a412134afe7/tools/clang/tools/dxcompiler/dxcdisassembler.cpp#L106

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12513>
 2021-08-25 20:19:05 +00:00
Michael Tang 62c3492d0b microsoft/compiler: Add support for SV_SampleIndex intrinsic 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12513>
 2021-08-25 20:19:05 +00:00
Alyssa Rosenzweig c4b5921d55 pan/bi: Fix format specifiers in disassembler 
Flagged by cppcheck.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
 2021-08-25 20:03:08 +00:00
Alyssa Rosenzweig 589f365d05 pan/bi: Remove unused clause_start field 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
 2021-08-25 20:03:08 +00:00
Alyssa Rosenzweig 1c2bc67fac pan/bi: Assert l != NULL in bi_ra 
Confuses cppcheck; indeed, the proof is confusing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
 2021-08-25 20:03:08 +00:00
Alyssa Rosenzweig b1aa15d582 pan/bi: Simplify condition 
Flagged by cppcheck.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
 2021-08-25 20:03:08 +00:00
Alyssa Rosenzweig c08423699c panfrost: Remove unused functions 
Flagged by cppcheck.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
 2021-08-25 20:03:08 +00:00
Alyssa Rosenzweig e9afd245f4 panfrost: Remove stale TODOs and XXXs 
These don't meaningfully apply but their comments never got updated.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
 2021-08-25 20:03:08 +00:00
Alyssa Rosenzweig 8f25a606b4 panfrost: Remove CACHE_LINE_SIZE #define 
Not only is it unused, it's totally wrong. Not even a little right.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
 2021-08-25 20:03:08 +00:00
Erik Faye-Lund 6e05f68924 llvmpipe: rip out cylindrical wrap support 
Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
 2021-08-25 19:37:16 +00:00
Erik Faye-Lund e9cc7f1ae4 softpipe: rip out cylindrical wrap support 
This is never used, so let's just remove it.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
 2021-08-25 19:37:16 +00:00
Erik Faye-Lund 7b0bda2e55 gallium/tgsi: rip out cylindrical wrap support 
We never enable this feature, so let's rip it out completely.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
 2021-08-25 19:37:16 +00:00