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intel: Support Tile4/64 in depth/stencil state

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Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
This commit is contained in:
Nanley Chery
2018-11-02 14:47:37 -07:00
committed by Marge Bot
parent f54de77c3a
commit dd9ae2dc7b
2 changed files with 28 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/genxml/gen125.xml
+8 -11
View File
@@ -1692,10 +1692,9 @@
<field name="Minimum Array Element" start="168" end="178" type="uint"/>
<field name="Depth" start="180" end="190" type="uint"/>
<field name="Mip Tail Start LOD" start="218" end="221" type="uint"/>
<field name="Tiled Resource Mode" start="222" end="223" type="uint">
<value name="NONE" value="0"/>
<value name="TILEYF" value="1"/>
<value name="TILEYS" value="2"/>
<field name="Tiled Mode" start="222" end="223" type="uint">
<value name="TILE64" value="1"/>
<value name="TILE4" value="3"/>
</field>
<field name="Surface QPitch" start="224" end="238" type="uint"/>
<field name="LOD" start="240" end="243" type="uint"/>
@@ -1977,10 +1976,9 @@
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Surface Pitch" start="32" end="48" type="uint"/>
<field name="Hierarchical Depth Buffer Write Thru Enable" start="52" end="52" type="bool"/>
<field name="Tiled Resource Mode" start="54" end="55" type="uint">
<value name="NONE" value="0"/>
<value name="TILEYF" value="1"/>
<value name="TILEYS" value="2"/>
<field name="Tiled Mode" start="54" end="55" type="uint">
<value name="TILE64" value="1"/>
<value name="TILE4" value="3"/>
</field>
<field name="MOCS" start="57" end="63" type="uint"/>
<field name="Hierarchical Depth Buffer MOCS" start="57" end="63" type="uint"/>
@@ -2755,9 +2753,8 @@
<field name="Depth" start="180" end="190" type="uint"/>
<field name="Mip Tail Start LOD" start="218" end="221" type="uint"/>
<field name="Tiled Mode" start="222" end="223" type="uint">
<value name="NONE" value="0"/>
<value name="TILEYF" value="1"/>
<value name="TILEYS" value="2"/>
<value name="TILE64" value="1"/>
<value name="TILE4" value="3"/>
</field>
<field name="Surface QPitch" start="224" end="238" type="uint"/>
<field name="Surf LOD" start="240" end="243" type="uint"/>
src/intel/isl/isl_emit_depth_stencil.c
+20 -1
View File
@@ -58,6 +58,13 @@ static const uint32_t isl_encode_ds_surftype[] = {
[ISL_SURF_DIM_3D] = SURFTYPE_3D,
};
#if GFX_VERx10 >= 125
static const uint8_t isl_encode_tiling[] = {
[ISL_TILING_4] = TILE4,
[ISL_TILING_64] = TILE64,
};
#endif
void
isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
const struct isl_depth_stencil_hiz_emit_info *restrict info)
@@ -115,7 +122,10 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
db.MOCS = info->mocs;
#endif
#if GFX_VER <= 6
#if GFX_VERx10 >= 125
db.TiledMode = isl_encode_tiling[info->depth_surf->tiling];
db.MipTailStartLOD = 15;
#elif GFX_VER <= 6
db.TiledSurface = info->depth_surf->tiling != ISL_TILING_LINEAR;
db.TileWalk = info->depth_surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
TILEWALK_XMAJOR;
@@ -156,6 +166,10 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
#if GFX_VER >= 7 && GFX_VER < 12
db.StencilWriteEnable = true;
#endif
#if GFX_VERx10 >= 125
sb.TiledMode = isl_encode_tiling[info->stencil_surf->tiling];
sb.MipTailStartLOD = 15;
#endif
#if GFX_VER >= 12
sb.StencilWriteEnable = true;
sb.SurfaceType = SURFTYPE_2D;
@@ -213,6 +227,11 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
hiz.SurfaceBaseAddress = info->hiz_address;
hiz.MOCS = info->mocs;
hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1;
#if GFX_VERx10 >= 125
hiz.TiledMode = isl_encode_tiling[info->hiz_surf->tiling];
#endif
#if GFX_VER >= 12
hiz.HierarchicalDepthBufferWriteThruEnable =
info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS_WT;