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Rob Clark bcf4c8893c freedreno/registers: Fix GRAS_LRZ_CNTL definition 
Two fields moved to GRAS_LRZ_CNTL2 on a7xx+.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:57 +00:00
Rob Clark f47c3d554b freedreno/registers: Name HYSTERESIS regs 
It looks like we'll need to program them for gen8.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:57 +00:00
Rob Clark 843ec5dbe7 freedreno/registers: Name RB_LRZ_CNTL2 
We'll need this for LRZ flush sequence on gen8

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:56 +00:00
Rob Clark 5c1bcaca24 freedreno/registers: Rename SP_HLSQ_MODE_CNTL 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:55 +00:00
Rob Clark 30a0ac7c0f freedreno/registers: Fix a few field names 
Give proper names to a few bitfields that we were already using.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:54 +00:00
Rob Clark ccdd5eb49d freedreno/decode: Add extra indent levels 
Now we start hitting an extra indent level.

Fixes: d7db333b0e ("freedreno/decode: Add gen8 support")
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:53 +00:00
Rob Clark e7a01c9c23 freedreno/decode: Print mode for compute shaders 
Similar to draw packets, it is useful to be able to see the mode and
pipe.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:53 +00:00
Rob Clark c026a8f105 freedreno/decode: Fix bindless descriptor dumping 
We shouldn't be trying to calculate an offset from the bindless base reg
we looked up, as it already contains the array index.

We could lookup the index 0 reg offset, and calculate an offset from
there, but that breaks when the registers are not consecutive.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:52 +00:00
Rob Clark f64e4a6d3e freedreno/a6xx: Fix debug comment 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:52 +00:00
Rob Clark 8480f32cfa freedreno/a6xx: Add helpers for preamble const loads 
Consolidate the logic about which path to take in one place.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:51 +00:00
Rob Clark bafcdbf375 freedreno/a6xx: Add helper to set render mode 
Make it less awkward to deal with gen6/7 vs gen8 differences.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:51 +00:00
Rob Clark b1218926bc freedreno/a6xx: Actually use lrz fast clear 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:50 +00:00
Rob Clark d30a14b726 freedreno/a6xx: Be more precise about CP_SET_MARKER 
Set the mode before we start emitting registers.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:50 +00:00
Rob Clark e0b6f97b9c freedreno/a6xx: Split preamble for gmem vs sysmem 
Possibly overkill currently, if we only preempt on bin boundaries.  But
might as well be complete in case that ever changes on the kernel side.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:49 +00:00
Rob Clark 701eb1ce8d freedreno/a6xx: Emit RB buffer setup for sysmem too 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:49 +00:00
Rob Clark 4ca78a296f freedreno/a6xx: Rework where we emit ccu cache cntl 
We don't need to re-emit it each tile.  But we do need to setup the
preemption to restore us to GMEM mode in case we get preempted on a tile
boundary.

While we are at it, rename the function to something more sensible.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:48 +00:00
Rob Clark 2439606518 freedreno/a6xx: Drop fd6_emit_blit() 
Now that we've corrected the event name (ie. CCU_RESOLVE to trigger the
resolve/unresolve engine) the helper name made less sense.  And it
doesn't really add any value.  So drop it.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:48 +00:00
Rob Clark d7850b26b6 freedreno/a6xx: Drop emit_marker6() 
For a6xx+ devcoredump+crashdec does a good job in finding the CP
position on a crash.  I don't really use the scratch regs for this
purpose anymore.  So lets just drop this.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:47 +00:00
Rob Clark 791cb33da5 freedreno/a6xx: Pass cs to fd6_clear_lrz() 
Make it more obvious that all the clears go in the prologue.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:47 +00:00
Rob Clark 1a22daa157 freedreno: More ergonomic cs casting 
Make it less awkward to bridge back to legacy cmdstream builder.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:46 +00:00
Rob Clark a24f3efd98 freedreno/a6xx: Add RB_DBG_ECO_MODE helper 
Avoid sprinkling the logic for blit vs non-blit values everywhere.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:46 +00:00
Rob Clark 56015d8cd9 freedreno/decode: Drop summary override for CRB 
It is just normal reg writes, we shouldn't handle it specially or
surpress summary state if enabled.  In summary mode we shouldn't print
each individual register write, but just show the values at draw/etc
time.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:45 +00:00
Rob Clark b8fd1e2f7c freedreno/a6xx: genx helper for additional template param 
In a few cases we have a 2nd template param.  Add a helper for this so
adding new gens is less awkward.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:44 +00:00
Rob Clark fb6dccc64c freedreno: flip template param order 
Prep for next patch.  We need the per-gen CHIP template param to be
last.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:44 +00:00
Rob Clark b2349354e3 freedreno/a6xx: Use with_crb() helper 
Small cleanup that was missed when introducing the helper.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:44 +00:00
Rob Clark 392293ce48 freedreno/a6xx: Move VFD_RENDER_MODE emit 
The other two regs with RENDER_MODE fields are already part of
set_bin_size().

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:43 +00:00
Rob Clark 9e0942d4d9 freedreno/registers: Move FLAGS_REGID 
This field is only in SP_GS_OUTPUT_CNTL, and not the other regs that
re-use the same bitset.  So move it there.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:43 +00:00
Rob Clark 6233b5d841 freedreno/registers: Event cleanups 
Cleanup variants ranges, and in a couple cases rename events to match
docs.  In some cases events are marked valid thru A5XX, simply to
indicate that they were removed at some unknown point before A6XX.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:42 +00:00
Rob Clark eeaf438911 freedreno/registers: Convert events to hex 
To match internal docs.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:40 +00:00
Rob Clark 74e77ce6a4 freedreno/crashdec: Log IBs to snapshot 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:39 +00:00
Rob Clark 8c372e8617 freedreno/crashdec: Dump cmdstream at end 
With gen8 we need to decode more sections before we have enough CP reg
vals to decode cmdstream.  So simplify things by just moving it to the
end.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:39 +00:00
Danylo Piliaiev 40b21f115d tu: Add custom resolve tracepoints 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38451>
 2025-12-08 20:44:47 +00:00
Connor Abbott 520e3f3a47 tu: Implement VK_EXT_custom_resolve 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38451>
 2025-12-08 20:44:46 +00:00
Connor Abbott ad84ae2719 tu: Implement VK_QCOM_subpass_shader_resolve 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38451>
 2025-12-08 20:44:46 +00:00
Connor Abbott 7691f1b70d ir3: Support addr0 align of 8 
At this point it isn't actually an alignment, but we need to multiply by
8 now because there are 2 vec4's per view for FDM driver params.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38451>
 2025-12-08 20:44:45 +00:00
Connor Abbott bd821b9a17 nir, tu: Add and use load_frag_coord_gmem_ir3 
We used load_frag_coord_unscaled_ir3 for loading the fragment coord for
input attachments in GMEM, where the normal scaling for gl_FragCoord
shouldn't be used. However with custom resolve a different scaling will
apply to attachments in GMEM. Separate "unscaled" from "gmem" and rename
the NIR options, in preparation for this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38451>
 2025-12-08 20:44:45 +00:00
Connor Abbott cd1e784148 tu: Fix FragCoord offset when HW viewport offset is enabled 
FragCoord seems to have the offset applied to it, so we don't need to
subtract it out. Fixes upcoming test
dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.custom_resolve.monolithic.fdm_nonsubsampled_multiview_with_offset.

Fixes: b34b089ca1 ("tu: Use GRAS bin offset registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38451>
 2025-12-08 20:44:45 +00:00
Connor Abbott b2c685af42 tu: Fix GRAS_BIN_FOVEAT* programming with more than 1 layer 
Similar to when patching load/store coordinates, we have to convert the
layer to the view, splatting view 0 to all layers when there is more
than 1 layer and FDM-per-layer is not enabled.

Fixes upcoming new test
dEQP-VK.renderpasses.*.custom_resolve.*.fdm_nonsubsampled_multilayer_with_offset.

Fixes: b34b089ca1 ("tu: Use GRAS bin offset registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38451>
 2025-12-08 20:44:45 +00:00
Calder Young ee42a48984 anv: Fix scratch pool buffer allocation sizes 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
CC: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38840>
 2025-12-08 20:09:57 +00:00
Yiwei Zhang 2de8981351 nir: suppress clang warnings for cooperative matrix lowering 
This suppresses below compile warnings:
- warning: variable 'idx' is used uninitialized whenever 'if' condition
  is false [-Wsometimes-uninitialized]

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38835>
 2025-12-08 19:36:05 +00:00
Natalie Vock 6d799ac283 aco: Add pass for spilling call-related registers 
This is a post-RA pass that tracks registers that are preserved by the
ABI, but clobbered by shader code. The pass inserts scratch spills and
reloads in appropriate locations to ensure the register values at the
end of the shader are the same as they were at the start.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:55 +00:00
Natalie Vock 93a5919cee aco/util: Add aco::unordered_set 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:55 +00:00
Natalie Vock 0cfabe0613 aco/lower_to_hw_instr: Add scratch size in call lowering 
We did this in the preserved spiller previously, but let's move it here.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:55 +00:00
Natalie Vock 7059068b61 aco/spill: Restore registers spilled by call immediately 
Makes for better latency hiding if we're not short on registers
otherwise.

On top of RT function calls:
Totals from 7 (0.01% of 81072) affected shaders:

Instrs: 9084 -> 8980 (-1.14%)
CodeSize: 52564 -> 51976 (-1.12%)
SpillSGPRs: 244 -> 248 (+1.64%); split: -3.28%, +4.92%
SpillVGPRs: 360 -> 367 (+1.94%)
Latency: 138989 -> 135669 (-2.39%); split: -2.49%, +0.10%
InvThroughput: 35120 -> 35301 (+0.52%); split: -0.06%, +0.57%
VClause: 258 -> 241 (-6.59%)
SClause: 116 -> 117 (+0.86%)
Copies: 1290 -> 1311 (+1.63%)
Branches: 131 -> 119 (-9.16%)
VALU: 6125 -> 6143 (+0.29%); split: -0.20%, +0.49%
SALU: 920 -> 913 (-0.76%); split: -0.98%, +0.22%
VMEM: 1026 -> 989 (-3.61%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:55 +00:00
Natalie Vock 6616f25e43 aco/spill: Create linear VGPRs for spilling ABI-preserved SGPRs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:55 +00:00
Natalie Vock 6b2e766617 aco/ra: Handle linear VGPRs allocated by p_startpgm 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:54 +00:00
Natalie Vock 761efe9163 aco/spill: Reset scratch_rsrc on calls 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:54 +00:00
Natalie Vock 369a3c0dca aco/spill: Handle calls 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:54 +00:00
Natalie Vock ecc548cd37 aco: Record required call spills during live-var analysis 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:53 +00:00
Natalie Vock 8bc5fdef53 aco: Remove unused p_reload_preserved def 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:52 +00:00