AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

freedreno/a6xx: Drop emit_marker6()

Browse Source 
For a6xx+ devcoredump+crashdec does a good job in finding the CP
position on a crash.  I don't really use the scratch regs for this
purpose anymore.  So lets just drop this.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark
2025-11-03 08:44:42 -08:00
committed by Marge Bot
parent 791cb33da5
commit d7850b26b6
5 changed files with 0 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/freedreno/a6xx/fd6_context.h
-12
View File
@@ -165,18 +165,6 @@ struct fd6_control {
#define control_ptr(fd6_ctx, member) \
(fd6_ctx)->control_mem, offsetof(struct fd6_control, member)
template <chip CHIP>
static inline void
emit_marker6(fd_cs &cs, int scratch_idx)
{
extern int32_t marker_cnt;
if (__EMIT_MARKER) {
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
fd_pkt4(cs, 1)
.add(CP_SCRATCH_REG(CHIP, scratch_idx, p_atomic_inc_return(&marker_cnt)));
}
}
struct fd6_vertex_stateobj {
struct fd_vertex_stateobj base;
struct fd_ringbuffer *stateobj;
src/gallium/drivers/freedreno/a6xx/fd6_draw.cc
-10
View File
@@ -479,14 +479,6 @@ draw_vbos(struct fd_context *ctx, const struct pipe_draw_info *info,
fd6_barrier_flush<CHIP>(cs, ctx->batch);
/* for debug after a lock up, write a unique counter value
* to scratch7 for each draw, to make it easier to match up
* register dumps to cmdstream. The combination of IB
* (scratch6) and DRAW is enough to "triangulate" the
* particular draw that caused lockup.
*/
emit_marker6<CHIP>(cs, 7);
if (is_indirect(DRAW)) {
assert(num_draws == 1); /* only >1 for direct draws */
if (DRAW == DRAW_INDIRECT_OP_XFB) {
@@ -551,8 +543,6 @@ draw_vbos(struct fd_context *ctx, const struct pipe_draw_info *info,
}
}
emit_marker6<CHIP>(cs, 7);
flush_streamout<CHIP>(ctx, cs, &emit);
fd_context_all_clean(ctx);
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
-2
View File
@@ -558,8 +558,6 @@ fd6_emit_3d_state(fd_cs &cs, struct fd6_emit *emit)
const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
const struct ir3_shader_variant *fs = emit->fs;
emit_marker6<CHIP>(cs, 5);
/* Special case, we need to re-emit bindless FS state w/ the
* fb-read state appended:
*/
src/gallium/drivers/freedreno/a6xx/fd6_emit.h
-6
View File
@@ -285,9 +285,7 @@ template <chip CHIP>
static inline void
fd6_emit_blit(struct fd_context *ctx, fd_cs &cs)
{
emit_marker6<CHIP>(cs, 7);
fd6_event_write<CHIP>(ctx, cs, FD_CCU_RESOLVE);
emit_marker6<CHIP>(cs, 7);
}
template <chip CHIP>
@@ -402,8 +400,6 @@ fd6_emit_ib(fd_cs &cs, struct fd_ringbuffer *target)
unsigned count = fd_ringbuffer_cmd_count(target);
emit_marker6<CHIP>(cs, 6);
for (unsigned i = 0; i < count; i++) {
uint32_t dwords;
@@ -413,8 +409,6 @@ fd6_emit_ib(fd_cs &cs, struct fd_ringbuffer *target)
assert(dwords > 0);
}
emit_marker6<CHIP>(cs, 6);
}
#endif /* FD6_EMIT_H */
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
-12
View File
@@ -809,8 +809,6 @@ emit_conditional_ib(fd_cs &cs, struct fd_batch *batch, const struct fd_tile *til
if (target->cur == target->start)
return;
emit_marker6<CHIP>(cs, 6);
unsigned count = fd_ringbuffer_cmd_count(target);
BEGIN_RING(cs, 5 + 4 * count); /* ensure conditional doesn't get split */
@@ -835,8 +833,6 @@ emit_conditional_ib(fd_cs &cs, struct fd_batch *batch, const struct fd_tile *til
assert(dwords > 0);
}
emit_marker6<CHIP>(cs, 6);
}
template <chip CHIP>
@@ -929,10 +925,8 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt
set_scissor<CHIP>(cs, 0, 0, gmem->width - 1, gmem->height - 1);
emit_marker6<CHIP>(cs, 7);
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_VISIBILITY));
emit_marker6<CHIP>(cs, 7);
fd_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1)
.add(0x1);
@@ -1213,11 +1207,9 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
struct fd6_context *fd6_ctx = fd6_context(ctx);
fd_cs cs(batch->gmem);
emit_marker6<CHIP>(cs, 7);
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_RENDER_START) |
A6XX_CP_SET_MARKER_0_USES_GMEM);
emit_marker6<CHIP>(cs, 7);
uint32_t x1 = tile->xoff;
uint32_t y1 = tile->yoff;
@@ -1864,10 +1856,8 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
fd_pkt7(cs, CP_SKIP_IB2_ENABLE_LOCAL, 1)
.add(0x0);
emit_marker6<CHIP>(cs, 7);
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0(.mode = RM6_BIN_RESOLVE, .uses_gmem = true));
emit_marker6<CHIP>(cs, 7);
if (batch->tile_store) {
trace_start_tile_stores(&batch->trace, cs, batch->resolve);
@@ -2029,10 +2019,8 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
crb.add(VPC_SO_OVERRIDE(CHIP, false));
}
emit_marker6<CHIP>(cs, 7);
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM6_DIRECT_RENDER));
emit_marker6<CHIP>(cs, 7);
fd_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1)
.add(0x0);