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freedreno/registers: Rename SP_HLSQ_MODE_CNTL

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Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark
2025-10-20 10:51:54 -07:00
committed by Marge Bot
parent 30a0ac7c0f
commit 5c1bcaca24
2 changed files with 8 additions and 6 deletions
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10
src/freedreno/common/freedreno_devices.py
View File

@@ -1044,7 +1044,7 @@ a730_raw_magic_regs = [
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080],
[A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_MODE_CNTL, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],
@@ -1096,7 +1096,7 @@ a740_raw_magic_regs = [
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080],
[A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_MODE_CNTL, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],
@@ -1196,7 +1196,7 @@ add_gpus([
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080],
[A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_MODE_CNTL, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],
@@ -1279,7 +1279,7 @@ add_gpus([
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080],
[A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_MODE_CNTL, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],
@@ -1360,7 +1360,7 @@ add_gpus([
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080],
[A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_MODE_CNTL, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],

4
src/freedreno/registers/adreno/a6xx.xml
View File

@@ -4134,7 +4134,9 @@ by a particular renderpass/blit.
</reg32>
<reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/>
<reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/>
<reg32 offset="0xab02" name="SP_HLSQ_MODE_CNTL" variants="A7XX-" usage="cmd">
<bitfield name="SHARED_CONSTS_ENABLE" pos="0" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->
</reg32>
<reg32 offset="0xab04" name="SP_PS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
<reg32 offset="0xab05" name="SP_PS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/>