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freedreno/registers: Event cleanups

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Cleanup variants ranges, and in a couple cases rename events to match
docs.  In some cases events are marked valid thru A5XX, simply to
indicate that they were removed at some unknown point before A6XX.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark
2025-10-15 10:06:54 -07:00
committed by Marge Bot
parent eeaf438911
commit 6233b5d841
14 changed files with 99 additions and 100 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/freedreno/common/freedreno_gpu_event.h
+9 -9
View File
@@ -47,7 +47,7 @@ enum fd_gpu_event : uint32_t {
FD_LRZ_INVALIDATE,
FD_VSC_BINNING_START,
FD_VSC_BINNING_END,
FD_BLIT,
FD_CCU_RESOLVE,
FD_LABEL,
FD_DUMMY_EVENT,
@@ -85,13 +85,13 @@ constexpr inline struct fd_gpu_event_info fd_gpu_events<A6XX>[FD_GPU_EVENT_MAX]
{PC_CCU_FLUSH_DEPTH_TS, true}, /* FD_CCU_CLEAN_DEPTH */
{PC_CCU_FLUSH_COLOR_TS, true}, /* FD_CCU_CLEAN_COLOR */
{LRZ_CLEAR, false}, /* FD_LRZ_CLEAR */
{LRZ_FLUSH, false}, /* FD_LRZ_FLIP */
{LRZ_FLUSH, false}, /* FD_LRZ_FLUSH */
{LRZ_CACHE_INVALIDATE, false}, /* FD_LRZ_INVALIDATE */
{DEBUG_LABEL, false}, /* FD_LRZ_FLIP */
{LRZ_FLUSH_INVALIDATE, false}, /* FD_LRZ_FLUSH */
{DEBUG_LABEL, false}, /* FD_LRZ_INVALIDATE */
{VSC_BINNING_START, false}, /* FD_VSC_BINNING_START */
{VSC_BINNING_END, false}, /* FD_VSC_BINNING_END */
{BLIT, false}, /* FD_BLIT */
{LABEL, false}, /* FD_LABEL */
{CCU_RESOLVE, false}, /* FD_CCU_RESOLVE */
{DEBUG_LABEL, false}, /* FD_LABEL */
};
template <>
@@ -118,12 +118,12 @@ constexpr inline struct fd_gpu_event_info fd_gpu_events<A7XX>[FD_GPU_EVENT_MAX]
{CCU_CLEAN_COLOR, false}, /* FD_CCU_CLEAN_COLOR */
{LRZ_CLEAR, false}, /* FD_LRZ_CLEAR */
{LRZ_FLIP_BUFFER, false}, /* FD_LRZ_FLIP */
{LRZ_FLUSH, false}, /* FD_LRZ_FLUSH */
{LRZ_CACHE_FLUSH, false}, /* FD_LRZ_FLUSH */
{LRZ_CACHE_INVALIDATE, false}, /* FD_LRZ_INVALIDATE */
{VSC_BINNING_START, false}, /* FD_VSC_BINNING_START */
{VSC_BINNING_END, false}, /* FD_VSC_BINNING_END */
{BLIT, false}, /* FD_BLIT */
{LABEL, false}, /* FD_LABEL */
{CCU_RESOLVE, false}, /* FD_CCU_RESOLVE */
{DEBUG_LABEL, false}, /* FD_LABEL */
{DUMMY_EVENT, false}, /* FD_DUMMY_EVENT */
};
src/freedreno/decode/cffdec.c
+1 -1
View File
@@ -2074,7 +2074,7 @@ cp_event_write(uint32_t *dwords, uint32_t sizedwords, int level)
if (name && (options->info->chip > 5)) {
char eventname[64];
snprintf(eventname, sizeof(eventname), "EVENT:%s", name);
if (!strcmp(name, "BLIT") || !strcmp(name, "LRZ_CLEAR")) {
if (!strcmp(name, "CCU_RESOLVE") || !strcmp(name, "LRZ_CLEAR")) {
do_query(eventname, 0);
print_mode(level);
dump_register_summary(level);
src/freedreno/decode/scripts/parse-submits.lua
+2 -2
View File
@@ -197,7 +197,7 @@ function CP_SET_MARKER(pkt, size)
end
function CP_EVENT_WRITE(pkt, size)
if tostring(pkt[0].EVENT) ~= "BLIT" then
if tostring(pkt[0].EVENT) ~= "CCU_RESOLVE" then
return
end
nullbatch = false
@@ -315,7 +315,7 @@ function draw(primtype, nindx)
if primtype == "BLIT_OP_SCALE" then
handle_blit()
return
elseif primtype == "EVENT:BLIT" then
elseif primtype == "EVENT:CCU_RESOLVE" then
return
end
src/freedreno/registers/adreno/adreno_pm4.xml
+22 -23
View File
@@ -6,10 +6,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="adreno/adreno_common.xml"/>
<enum name="vgt_event_type" varset="chip">
<value name="VS_DEALLOC" value="0x00"/>
<value name="PS_DEALLOC" value="0x01" variants="A2XX-A6XX"/>
<value name="VS_DONE_TS" value="0x02"/>
<value name="PS_DONE_TS" value="0x03"/>
<value name="VS_DEALLOC" value="0x00" variants="A2XX-A5XX"/>
<value name="PS_DEALLOC" value="0x01" variants="A2XX-A5XX"/>
<value name="VS_DONE_TS" value="0x02" variants="A2XX-A5XX"/>
<value name="PS_DONE_TS" value="0x03" variants="A2XX-A5XX"/>
<doc>
Flushes dirty data from UCHE, and also writes a GPU timestamp to
the address if one is provided.
@@ -46,11 +46,11 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="PERFCOUNTER_START" value="0x17" variants="A2XX-A4XX"/>
<value name="PERFCOUNTER_STOP" value="0x18" variants="A2XX-A4XX"/>
<value name="VS_FETCH_DONE" value="0x1b"/>
<value name="VS_FETCH_DONE" value="0x1b" variants="A2XX-A5XX"/>
<value name="FACENESS_FLUSH" value="0x1c" variants="A2XX-A4XX"/>
<!-- a5xx events -->
<value name="WT_DONE_TS" value="0x08" variants="A5XX-"/>
<value name="WT_DONE_TS" value="0x08" variants="A5XX-A6XX"/>
<value name="START_FRAGMENT_CTRS" value="0x0d" variants="A5XX-"/>
<value name="STOP_FRAGMENT_CTRS" value="0x0e" variants="A5XX-"/>
<value name="START_COMPUTE_CTRS" value="0x0f" variants="A5XX-"/>
@@ -64,13 +64,13 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
Invalidates depth attachment data from the CCU. We assume this
happens in the last stage.
</doc>
<value name="PC_CCU_INVALIDATE_DEPTH" value="0x18" variants="A5XX-"/>
<value name="PC_CCU_INVALIDATE_DEPTH" value="0x18" variants="A5XX-A6XX"/>
<doc>
Invalidates color attachment data from the CCU. We assume this
happens in the last stage.
</doc>
<value name="PC_CCU_INVALIDATE_COLOR" value="0x19" variants="A5XX-"/>
<value name="PC_CCU_INVALIDATE_COLOR" value="0x19" variants="A5XX-A6XX"/>
<doc>
Flushes the small cache used by CP_EVENT_WRITE::BLIT (which,
@@ -82,20 +82,19 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
Flushes depth attachment data from the CCU. We assume this
happens in the last stage.
</doc>
<value name="PC_CCU_FLUSH_DEPTH_TS" value="0x1c" variants="A5XX-"/>
<value name="PC_CCU_FLUSH_DEPTH_TS" value="0x1c" variants="A5XX-A6XX"/>
<doc>
Flushes color attachment data from the CCU. We assume this
happens in the last stage.
</doc>
<value name="PC_CCU_FLUSH_COLOR_TS" value="0x1d" variants="A5XX-"/>
<value name="PC_CCU_FLUSH_COLOR_TS" value="0x1d" variants="A5XX-A6XX"/>
<doc>
2D blit to resolve GMEM to system memory (skipping CCU) at the
end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for
more general blitting.
Triggers a resolve (GMEM to sysmem) or unresolve (sysmem to
GMEM) or clear blit, depending on CCU programming.
</doc>
<value name="BLIT" value="0x1e" variants="A5XX-"/>
<value name="CCU_RESOLVE" value="0x1e" variants="A5XX-"/>
<doc>
Flip between the primary and secondary LRZ buffers. This is used
@@ -117,8 +116,9 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
</doc>
<value name="LRZ_CLEAR" value="0x25" variants="A5XX-"/>
<value name="LRZ_FLUSH" value="0x26" variants="A5XX-"/>
<value name="BLIT_OP_FILL_2D" value="0x27" variants="A5XX-"/>
<value name="LRZ_FLUSH_INVALIDATE" value="0x26" variants="A5XX-A6XX"/>
<value name="LRZ_CACHE_FLUSH" value="0x26" variants="A7XX-"/>
<value name="BLIT_OP_FILL_2D" value="0x27" variants="A5XX-A6XX"/>
<value name="BLIT_OP_COPY_2D" value="0x28" variants="A5XX-A6XX"/>
<value name="LRZ_CACHE_INVALIDATE" value="0x28" variants="A7XX-"/>
<value name="LRZ_Q_CACHE_INVALIDATE" value="0x29" variants="A7XX-"/>
@@ -133,7 +133,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
</doc>
<value name="CACHE_INVALIDATE" value="0x31" variants="A6XX"/>
<value name="LABEL" value="0x3f" variants="A6XX-"/>
<value name="DEBUG_LABEL" value="0x3f" variants="A6XX-"/>
<!-- note, some of these are the same as a6xx, just named differently -->
@@ -144,7 +144,6 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="CCU_RESOLVE_CLEAN" value="0x1a" variants="A7XX-"/>
<value name="CCU_FLUSH_DEPTH" value="0x1c" variants="A7XX-"/>
<value name="CCU_FLUSH_COLOR" value="0x1d" variants="A7XX-"/>
<value name="CCU_RESOLVE" value="0x1e" variants="A7XX-"/>
<value name="CCU_END_RESOLVE_GROUP" value="0x1f" variants="A7XX-"/>
<value name="CCU_CLEAN_DEPTH" value="0x20" variants="A7XX-"/>
<value name="CCU_CLEAN_COLOR" value="0x21" variants="A7XX-"/>
@@ -311,11 +310,11 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/>
<value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/>
<doc>generate a VS|PS_done event</doc>
<value name="CP_EVENT_WRITE_SHD" value="0x58"/>
<value name="CP_EVENT_WRITE_SHD" value="0x58" variants="A2XX"/>
<doc>generate a cache flush done event</doc>
<value name="CP_EVENT_WRITE_CFL" value="0x59"/>
<value name="CP_EVENT_WRITE_CFL" value="0x59" variants="A2XX"/>
<doc>generate a z_pass done event</doc>
<value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
<value name="CP_EVENT_WRITE_ZPD" value="0x5b" variants="A2XX"/>
<doc>
not sure the real name, but this seems to be what is used for
opencl, instead of CP_DRAW_INDX..
@@ -336,9 +335,9 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<doc>load constant into chip and to memory</doc>
<value name="CP_SET_CONSTANT" value="0x2d" variants="A2XX"/>
<doc>load sequencer instruction memory (pointer-based)</doc>
<value name="CP_IM_LOAD" value="0x27"/>
<value name="CP_IM_LOAD" value="0x27" variants="A2XX"/>
<doc>load sequencer instruction memory (code embedded in packet)</doc>
<value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
<value name="CP_IM_LOAD_IMMEDIATE" value="0x2b" variants="A2XX"/>
<doc>load constants from a location in memory</doc>
<value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
<doc>selective invalidation of state pointers</doc>
src/freedreno/tests/reference/afuc_test.asm
+5 -5
View File
@@ -181,13 +181,8 @@ CP_DRAW_PRED_ENABLE_LOCAL:
CP_DRAW_PRED_SET:
CP_END_BIN:
CP_EVENT_WRITE:
CP_EVENT_WRITE_CFL:
CP_EVENT_WRITE_SHD:
CP_EVENT_WRITE_ZPD:
CP_EXEC_CS:
CP_EXEC_CS_INDIRECT:
CP_IM_LOAD:
CP_IM_LOAD_IMMEDIATE:
CP_INDIRECT_BUFFER:
CP_INDIRECT_BUFFER_CHAIN:
CP_INDIRECT_BUFFER_PFD:
@@ -266,6 +261,8 @@ UNKN3:
UNKN30:
UNKN31:
UNKN32:
UNKN39:
UNKN43:
UNKN45:
UNKN48:
UNKN5:
@@ -274,8 +271,11 @@ UNKN6:
UNKN7:
UNKN73:
UNKN8:
UNKN88:
UNKN89:
UNKN9:
UNKN90:
UNKN91:
UNKN93:
UNKN96:
UNKN97:
src/freedreno/tests/reference/afuc_test_a7xx.asm
+15 -15
View File
@@ -209,15 +209,10 @@ CP_DRAW_PRED_ENABLE_LOCAL:
CP_DRAW_PRED_SET:
CP_END_BIN:
CP_EVENT_WRITE7:
CP_EVENT_WRITE_CFL:
CP_EVENT_WRITE_SHD:
CP_EVENT_WRITE_ZPD:
CP_EXEC_CS:
CP_EXEC_CS_INDIRECT:
CP_FIXED_STRIDE_DRAW_TABLE:
CP_GLOBAL_TIMESTAMP:
CP_IM_LOAD:
CP_IM_LOAD_IMMEDIATE:
CP_INDIRECT_BUFFER:
CP_INDIRECT_BUFFER_CHAIN:
CP_INDIRECT_BUFFER_PFD:
@@ -296,14 +291,19 @@ UNKN2:
UNKN3:
UNKN30:
UNKN32:
UNKN39:
UNKN43:
UNKN48:
UNKN5:
UNKN6:
UNKN7:
UNKN8:
UNKN84:
UNKN88:
UNKN89:
UNKN9:
UNKN90:
UNKN91:
UNKN96:
UNKN97:
waitin
@@ -370,15 +370,10 @@ CP_DRAW_PRED_ENABLE_LOCAL:
CP_DRAW_PRED_SET:
CP_END_BIN:
CP_EVENT_WRITE7:
CP_EVENT_WRITE_CFL:
CP_EVENT_WRITE_SHD:
CP_EVENT_WRITE_ZPD:
CP_EXEC_CS:
CP_EXEC_CS_INDIRECT:
CP_FIXED_STRIDE_DRAW_TABLE:
CP_GLOBAL_TIMESTAMP:
CP_IM_LOAD:
CP_IM_LOAD_IMMEDIATE:
CP_INDIRECT_BUFFER:
CP_INDIRECT_BUFFER_CHAIN:
CP_INDIRECT_BUFFER_PFD:
@@ -467,14 +462,19 @@ UNKN2:
UNKN3:
UNKN30:
UNKN32:
UNKN39:
UNKN43:
UNKN48:
UNKN5:
UNKN6:
UNKN7:
UNKN8:
UNKN84:
UNKN88:
UNKN89:
UNKN9:
UNKN90:
UNKN91:
UNKN96:
UNKN97:
waitin
@@ -533,15 +533,10 @@ CP_DRAW_PRED_ENABLE_LOCAL:
CP_DRAW_PRED_SET:
CP_END_BIN:
CP_EVENT_WRITE7:
CP_EVENT_WRITE_CFL:
CP_EVENT_WRITE_SHD:
CP_EVENT_WRITE_ZPD:
CP_EXEC_CS:
CP_EXEC_CS_INDIRECT:
CP_FIXED_STRIDE_DRAW_TABLE:
CP_GLOBAL_TIMESTAMP:
CP_IM_LOAD:
CP_IM_LOAD_IMMEDIATE:
CP_INDIRECT_BUFFER:
CP_INDIRECT_BUFFER_CHAIN:
CP_INDIRECT_BUFFER_PFD:
@@ -630,14 +625,19 @@ UNKN2:
UNKN3:
UNKN30:
UNKN32:
UNKN39:
UNKN43:
UNKN48:
UNKN5:
UNKN6:
UNKN7:
UNKN8:
UNKN84:
UNKN88:
UNKN89:
UNKN9:
UNKN90:
UNKN91:
UNKN96:
UNKN97:
waitin
src/freedreno/tests/reference/compute-a540.log
+4 -4
View File
@@ -351,8 +351,8 @@ cmdstream[0]: 207 dwords
GRAS_LRZ_CNTL: { 0 }
000000050019020c: 0000: 48e10001 00000000
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = LRZ_FLUSH }
event LRZ_FLUSH
{ EVENT = LRZ_FLUSH_INVALIDATE }
event LRZ_FLUSH_INVALIDATE
0000000500190214: 0000: 70460001 00000026
opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
000000050019021c: 0000: 709d0001 00000000
@@ -855,8 +855,8 @@ cmdstream[0]: 207 dwords
GRAS_LRZ_CNTL: { 0x8 }
00000005001902c8: 0000: 48e10001 00000008
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = LRZ_FLUSH }
event LRZ_FLUSH
{ EVENT = LRZ_FLUSH_INVALIDATE }
event LRZ_FLUSH_INVALIDATE
00000005001902d0: 0000: 70460001 00000026
opcode: CP_EVENT_WRITE (46) (5 dwords)
{ EVENT = CACHE_FLUSH_TS }
src/freedreno/tests/reference/crash_prefetch.log
+16 -16
View File
@@ -8271,8 +8271,8 @@ got cmdszdw=38
{ DWORDS = 54 }
0000000100227000: 0000: 70c70002 34000000 00000036
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = BLIT }
event BLIT
{ EVENT = CCU_RESOLVE }
event CCU_RESOLVE
mode: RM6_DIRECT_RENDER
skip_ib2: g=0, l=0
draw[8] register values
@@ -8356,8 +8356,8 @@ got cmdszdw=38
+ 00080000 HLSQ_DBG_ECO_CNTL: 0x80000
0000000100227054: 0000: 70460001 0000001e
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = BLIT }
event BLIT
{ EVENT = CCU_RESOLVE }
event CCU_RESOLVE
mode: RM6_DIRECT_RENDER
skip_ib2: g=0, l=0
draw[9] register values
@@ -8371,8 +8371,8 @@ got cmdszdw=38
+ 00000003 RB_RESOLVE_OPERATION: { TYPE = BLIT_EVENT_LOAD | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
0000000100227098: 0000: 70460001 0000001e
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = BLIT }
event BLIT
{ EVENT = CCU_RESOLVE }
event CCU_RESOLVE
mode: RM6_DIRECT_RENDER
skip_ib2: g=0, l=0
draw[10] register values
@@ -8981,8 +8981,8 @@ got cmdszdw=38
{ DWORDS = 17 }
0000000100227250: 0000: 70c70002 10000000 00000011
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = BLIT }
event BLIT
{ EVENT = CCU_RESOLVE }
event CCU_RESOLVE
mode: RM6_DIRECT_RENDER
skip_ib2: g=0, l=0
draw[12] register values
@@ -9002,8 +9002,8 @@ got cmdszdw=38
{ DWORDS = 20 }
00000001002272a0: 0000: 70c70002 34000000 00000014
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = BLIT }
event BLIT
{ EVENT = CCU_RESOLVE }
event CCU_RESOLVE
mode: RM6_DIRECT_RENDER
skip_ib2: g=0, l=0
draw[13] register values
@@ -9666,8 +9666,8 @@ got cmdszdw=38
{ DWORDS = 17 }
0000000100227524: 0000: 70c70002 10000000 00000011
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = BLIT }
event BLIT
{ EVENT = CCU_RESOLVE }
event CCU_RESOLVE
mode: RM6_DIRECT_RENDER
skip_ib2: g=0, l=0
draw[16] register values
@@ -9687,8 +9687,8 @@ got cmdszdw=38
{ DWORDS = 20 }
0000000100227574: 0000: 70c70002 34000000 00000014
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = BLIT }
event BLIT
{ EVENT = CCU_RESOLVE }
event CCU_RESOLVE
mode: RM6_DIRECT_RENDER
skip_ib2: g=0, l=0
draw[17] register values
@@ -10974,8 +10974,8 @@ ESTIMATED CRASH LOCATION!
opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
000000010022332c: 0000: 709d0001 00000000
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = LRZ_FLUSH }
event LRZ_FLUSH
{ EVENT = LRZ_FLUSH_INVALIDATE }
event LRZ_FLUSH_INVALIDATE
0000000100223334: 0000: 70460001 00000026
opcode: CP_SET_DRAW_STATE (43) (4 dwords)
{ COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
src/freedreno/tests/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+8 -8
View File
@@ -352,8 +352,8 @@ cmdstream[0]: 265 dwords
+ 00000000 HLSQ_DBG_ECO_CNTL: 0
00000000010582dc: 0000: 702c0001 00000003
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = LRZ_FLUSH }
event LRZ_FLUSH
{ EVENT = LRZ_FLUSH_INVALIDATE }
event LRZ_FLUSH_INVALIDATE
00000000010582e4: 0000: 70460001 00000026
opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
00000000010582ec: 0000: 709d0001 00000000
@@ -459,8 +459,8 @@ cmdstream[0]: 265 dwords
RB_RESOLVE_GMEM_BUFFER_BASE: 0
000000000115e04c: 0000: 4088d601 00000000
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = BLIT }
event BLIT
{ EVENT = CCU_RESOLVE }
event CCU_RESOLVE
mode: RM6_BIN_RENDER_START
skip_ib2: g=0, l=0
draw[1] register values
@@ -1495,8 +1495,8 @@ cmdstream[0]: 265 dwords
RB_RESOLVE_GMEM_BUFFER_BASE: 0
000000000115c060: 0000: 4088d601 00000000
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = BLIT }
event BLIT
{ EVENT = CCU_RESOLVE }
event CCU_RESOLVE
mode: RM6_BIN_RESOLVE
skip_ib2: g=0, l=0
draw[3] register values
@@ -1516,8 +1516,8 @@ cmdstream[0]: 265 dwords
GRAS_LRZ_CNTL: { DIR = 0 }
00000000010583d8: 0000: 48810001 00000000
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = LRZ_FLUSH }
event LRZ_FLUSH
{ EVENT = LRZ_FLUSH_INVALIDATE }
event LRZ_FLUSH_INVALIDATE
00000000010583e0: 0000: 70460001 00000026
opcode: CP_EVENT_WRITE (46) (5 dwords)
{ EVENT = PC_CCU_RESOLVE_TS }
src/freedreno/tests/reference/fd-clouds.log
+6 -6
View File
@@ -232,8 +232,8 @@ cmdstream[0]: 1023 dwords
RB_LRZ_CNTL: { 0 }
0000000001d91258: 0000: 40889801 00000000
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = LRZ_FLUSH }
event LRZ_FLUSH
{ EVENT = LRZ_FLUSH_INVALIDATE }
event LRZ_FLUSH_INVALIDATE
0000000001d91260: 0000: 70460001 00000026
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = CACHE_INVALIDATE }
@@ -1577,8 +1577,8 @@ cmdstream[0]: 1023 dwords
:0,1,15,5
0000000001116114: 0000: 48088a01 00000005
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = BLIT }
event BLIT
{ EVENT = CCU_RESOLVE }
event CCU_RESOLVE
mode: RM6_BIN_RENDER_START
skip_ib2: g=1, l=0
draw[1] register values
@@ -6733,8 +6733,8 @@ cmdstream[0]: 1023 dwords
:0,1,21,7
0000000001116168: 0000: 48088a01 00000007
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = BLIT }
event BLIT
{ EVENT = CCU_RESOLVE }
event CCU_RESOLVE
mode: RM6_BIN_RESOLVE
skip_ib2: g=1, l=0
draw[3] register values
src/freedreno/tests/reference/prefetch-test.log
+6 -6
View File
@@ -8301,12 +8301,12 @@ got cmdszdw=416
{ [0].ADDR = 0 }
0000000103cd11ec: 0000: 70438003 00040000 00000000 00000000
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = LRZ_FLUSH }
event LRZ_FLUSH
{ EVENT = LRZ_FLUSH_INVALIDATE }
event LRZ_FLUSH_INVALIDATE
0000000103cd1314: 0000: 70460001 00000026
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = LABEL }
event LABEL
{ EVENT = DEBUG_LABEL }
event DEBUG_LABEL
0000000103cd13f0: 0000: 70460001 0000003f
opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000103cd13f8: 0000: 70268000
@@ -144457,8 +144457,8 @@ ESTIMATED CRASH LOCATION!
opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
000000010391f2a0: 0000: 709d0001 00000000
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = LRZ_FLUSH }
event LRZ_FLUSH
{ EVENT = LRZ_FLUSH_INVALIDATE }
event LRZ_FLUSH_INVALIDATE
000000010391f2a8: 0000: 70460001 00000026
opcode: CP_EVENT_WRITE (46) (5 dwords)
{ EVENT = PC_CCU_FLUSH_COLOR_TS }
src/freedreno/vulkan/tu_clear_blit.cc
+2 -2
View File
@@ -2036,7 +2036,7 @@ event_blit_run(struct tu_cmd_buffer *cmd,
}
}
tu_emit_event_write<CHIP>(cmd, cs, FD_BLIT);
tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_RESOLVE);
}
static void
@@ -4326,7 +4326,7 @@ clear_gmem_attachment(struct tu_cmd_buffer *cmd,
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_CLEAR_COLOR_DW0, 4);
tu_cs_emit_array(cs, clear_vals, 4);
tu_emit_event_write<CHIP>(cmd, cs, FD_BLIT);
tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_RESOLVE);
}
struct apply_gmem_clear_coords_state {
src/gallium/drivers/freedreno/a5xx/fd5_emit.h
+2 -2
View File
@@ -136,7 +136,7 @@ static inline void
fd5_emit_blit(struct fd_batch *batch, struct fd_ringbuffer *ring)
{
emit_marker5(ring, 7);
fd5_event_write(batch, ring, BLIT, true);
fd5_event_write(batch, ring, CCU_RESOLVE, true);
emit_marker5(ring, 7);
}
@@ -177,7 +177,7 @@ fd5_emit_lrz_flush(struct fd_batch *batch, struct fd_ringbuffer *ring)
OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
OUT_RING(ring, A5XX_GRAS_LRZ_CNTL_ENABLE);
fd5_event_write(batch, ring, LRZ_FLUSH, false);
fd5_event_write(batch, ring, LRZ_FLUSH_INVALIDATE, false);
OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
OUT_RING(ring, 0x0);
src/gallium/drivers/freedreno/a6xx/fd6_emit.h
+1 -1
View File
@@ -286,7 +286,7 @@ static inline void
fd6_emit_blit(struct fd_context *ctx, fd_cs &cs)
{
emit_marker6<CHIP>(cs, 7);
fd6_event_write<CHIP>(ctx, cs, FD_BLIT);
fd6_event_write<CHIP>(ctx, cs, FD_CCU_RESOLVE);
emit_marker6<CHIP>(cs, 7);
}