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freedreno/registers: Name HYSTERESIS regs

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It looks like we'll need to program them for gen8.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark
2025-10-20 12:00:49 -07:00
committed by Marge Bot
parent 843ec5dbe7
commit f47c3d554b
5 changed files with 17 additions and 13 deletions
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src/freedreno/registers/adreno/a6xx.xml
+10 -6
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@@ -3653,6 +3653,10 @@ by a particular renderpass/blit.
<bitfield name="OFFSET" low="0" high="18" shr="11"/>
</bitset>
<bitset name="a6xx_sp_xs_hysteresis" inline="yes">
<doc>Same on a6xx/a7xx, UMD should not need to write this</doc>
</bitset>
<reg32 offset="0xa81b" name="SP_VS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/>
<reg64 offset="0xa81c" name="SP_VS_BASE" type="address" align="32" usage="rp_blit"/>
<reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
@@ -3662,7 +3666,7 @@ by a particular renderpass/blit.
<reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
<reg32 offset="0xa824" name="SP_VS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/>
<reg32 offset="0xa825" name="SP_VS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/>
<reg32 offset="0xa826" name="SP_UNKNOWN_A826"/>
<reg32 offset="0xa826" name="SP_VS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/>
<reg32 offset="0xa82d" name="SP_VS_VGS_CNTL" variants="A7XX-" usage="cmd"/>
<reg32 offset="0xa830" name="SP_HS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit">
@@ -3688,7 +3692,7 @@ by a particular renderpass/blit.
<reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
<reg32 offset="0xa83c" name="SP_HS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/>
<reg32 offset="0xa83d" name="SP_HS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/>
<reg32 offset="0xa83e" name="SP_HS_UNKNOWN_A83E"/>
<reg32 offset="0xa83e" name="SP_HS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/>
<reg32 offset="0xa82f" name="SP_HS_VGS_CNTL" variants="A7XX-" usage="cmd"/>
<reg32 offset="0xa840" name="SP_DS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit">
@@ -3726,7 +3730,7 @@ by a particular renderpass/blit.
<reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
<reg32 offset="0xa864" name="SP_DS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/>
<reg32 offset="0xa865" name="SP_DS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/>
<reg32 offset="0xa866" name="SP_DS_UNKNOWN_A866"/>
<reg32 offset="0xa866" name="SP_DS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/>
<reg32 offset="0xa868" name="SP_DS_VGS_CNTL" variants="A7XX-" usage="cmd"/>
<reg32 offset="0xa870" name="SP_GS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit">
@@ -3782,7 +3786,7 @@ by a particular renderpass/blit.
<reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
<reg32 offset="0xa895" name="SP_GS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/>
<reg32 offset="0xa896" name="SP_GS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/>
<reg32 offset="0xa897" name="SP_GS_UNKNOWN_A897"/>
<reg32 offset="0xa897" name="SP_GS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/>
<reg32 offset="0xa899" name="SP_GS_VGS_CNTL" variants="A7XX-" usage="cmd"/>
<reg64 offset="0xa8a0" name="SP_VS_SAMPLER_BASE" type="address" align="16" usage="cmd"/>
@@ -3933,7 +3937,7 @@ by a particular renderpass/blit.
<reg32 offset="0xa9a7" name="SP_PS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/>
<reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? -->
<reg32 offset="0xa9a9" name="SP_PS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/>
<reg32 offset="0xa9ab" name="SP_PS_UNKNOWN_A9AB" variants="A7XX-" usage="cmd"/>
<reg32 offset="0xa9ab" name="SP_PS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/>
<!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->
@@ -3985,7 +3989,7 @@ by a particular renderpass/blit.
<reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/>
<reg32 offset="0xa9bc" name="SP_CS_INSTR_SIZE" low="0" high="27" type="uint" usage="cmd"/>
<reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="cmd"/>
<reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/>
<reg32 offset="0xa9be" name="SP_CS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/>
<reg32 offset="0xa9c5" name="SP_CS_VGS_CNTL" variants="A7XX-" usage="cmd"/>
<!-- new in a6xx gen4, matches SP_CS_CONST_CONFIG_0 -->
src/freedreno/vulkan/tu_cmd_buffer.cc
+4 -4
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@@ -265,11 +265,11 @@ tu_emit_rt_workaround(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_RT_WA_START);
tu_cs_emit_regs(cs, SP_CS_UNKNOWN_A9BE(CHIP, .dword = 0x10000));
tu_cs_emit_regs(cs, SP_PS_UNKNOWN_A9AB(CHIP, .dword = 0x10000));
tu_cs_emit_regs(cs, SP_CS_HYSTERESIS(CHIP, .dword = 0x10000));
tu_cs_emit_regs(cs, SP_PS_HYSTERESIS(CHIP, .dword = 0x10000));
tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
tu_cs_emit_regs(cs, SP_CS_UNKNOWN_A9BE(CHIP, .dword = 0));
tu_cs_emit_regs(cs, SP_PS_UNKNOWN_A9AB(CHIP, .dword = 0));
tu_cs_emit_regs(cs, SP_CS_HYSTERESIS(CHIP, .dword = 0));
tu_cs_emit_regs(cs, SP_PS_HYSTERESIS(CHIP, .dword = 0));
tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
src/freedreno/vulkan/tu_device.cc
+1 -1
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@@ -2587,7 +2587,7 @@ tu_init_cmdbuf_start_a725_quirk(struct tu_device *device)
.linearlocalidregid = regid(63, 0),
.threadsize = THREAD128,
.workitemrastorder = WORKITEMRASTORDER_TILED));
tu_cs_emit_regs(&sub_cs, SP_CS_UNKNOWN_A9BE(A7XX, 0));
tu_cs_emit_regs(&sub_cs, SP_CS_HYSTERESIS(A7XX, 0));
tu_cs_emit_regs(&sub_cs,
SP_CS_NDRANGE_0(A7XX, .kerneldim = 3,
src/freedreno/vulkan/tu_shader.cc
+1 -1
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@@ -1859,7 +1859,7 @@ tu6_emit_cs_config(struct tu_cs *cs,
WORKITEMRASTORDER_LINEAR :
WORKITEMRASTORDER_TILED, ));
tu_cs_emit_regs(cs, SP_CS_UNKNOWN_A9BE(CHIP, 0)); // Sometimes is 0x08000000
tu_cs_emit_regs(cs, SP_CS_HYSTERESIS(CHIP, 0)); // Sometimes is 0x08000000
}
}
src/gallium/drivers/freedreno/a6xx/fd6_compute.cc
+1 -1
View File
@@ -144,7 +144,7 @@ cs_program_emit(struct fd_context *ctx, fd_crb &crb, struct ir3_shader_variant *
v->cs.force_linear_dispatch ? WORKITEMRASTORDER_LINEAR
: WORKITEMRASTORDER_TILED,
));
crb.add(SP_CS_UNKNOWN_A9BE(CHIP, 0)); // Sometimes is 0x08000000
crb.add(SP_CS_HYSTERESIS(CHIP, 0)); // Sometimes is 0x08000000
}
if (!v->local_size_variable)