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159440 Commits

Author SHA1 Message Date
Yonggang Luo f9860a84b3 compiler: Combine duplicated implementation of is_gl_identifier into glsl_types.h 
As glsl_types.cpp also called is_gl_identifier, so move it into glsl_types.h,
this will help the decouple glsl_types.h from src/compiler/glsl/*

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23420>
 2023-06-07 00:33:33 +00:00
Patrick Lerda 340311dac9 r600: fix r600_draw_vbo() buffer overflow 
The previous implementation was copying the data using the
aligned length (size_dw). The aligned length could overflow
the original buffer size.

For instance, this issue is triggered with "piglit/bin/draw-batch -auto -fbo":
==5736==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fff139c77e8 at pc 0x7f25b350a9a0 bp 0x7fff139c6cb0 sp 0x7fff139c6460
READ of size 8 at 0x7fff139c77e8 thread T0
    #0 0x7f25b350a99f in __interceptor_memcpy (/usr/lib64/libasan.so.6+0x3c99f)
    #1 0x7f25a8fcdf24 in radeon_emit_array ../src/gallium/include/winsys/radeon_winsys.h:760
    #2 0x7f25a8fcdf24 in r600_draw_vbo ../src/gallium/drivers/r600/r600_state_common.c:2448
    #3 0x7f25a8ae7ba1 in u_vbuf_draw_vbo ../src/gallium/auxiliary/util/u_vbuf.c:1791
    #4 0x7f25a7bc18ca in _mesa_validated_drawrangeelements ../src/mesa/main/draw.c:1696
    #5 0x7f25a7bc7e53 in _mesa_DrawElements ../src/mesa/main/draw.c:1824

Fixes: 0cf5d1f226 ("gallium: remove PIPE_CAP_INFO_START_WITH_USER_INDICES and fix all drivers")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23436>
 2023-06-06 23:16:05 +00:00
Vinson Lee ed759ad795 dzn: Fix qpool->queries_lock double lock 
Fix defect reported by Coverity Scan.

Double lock (LOCK)
double_lock: mtx_lock locks qpool->queries_lock while it is locked.

Fixes: a012b21964 ("microsoft: Initial vulkan-on-12 driver")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23455>
 2023-06-06 22:23:32 +00:00
Caio Oliveira 60664285a9 nir/print: Do not print raw values 
In many cases the raw value is not really helpful,
since we only work with enums and the raw value is
already printed for indices without special printing.

If an index benefits from having special printing AND the
raw value, we can include the printing of the raw value
as part of its handler.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23375>
 2023-06-06 21:50:34 +00:00
Mykhailo Skorokhodov 49c7fd7a7e iris: Fix memory size with disabled resizable bar 
When the resizable bar feature is disabled,
then vram.mappable.size is only 256MB.
The second half of the total size is in the vram.unmappable.size variable.

Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23402>
 2023-06-06 20:58:00 +00:00
Eric Engestrom 07207d12b0 ci/zink+radv: update expectations 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23465>
 2023-06-06 20:24:25 +00:00
Eric Engestrom 9316ab74ef ci/radv: update expectations 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23465>
 2023-06-06 20:24:24 +00:00
Alyssa Rosenzweig 99a00e2247 treewide: Use nir_trim_vector more 
Via Coccinelle patches

    @@
    expression a, b, c;
    @@

    -nir_channels(b, a, (1 << c) - 1)
    +nir_trim_vector(b, a, c)

    @@
    expression a, b, c;
    @@

    -nir_channels(b, a, BITFIELD_MASK(c))
    +nir_trim_vector(b, a, c)

    @@
    expression a, b;
    @@

    -nir_channels(b, a, 3)
    +nir_trim_vector(b, a, 2)

    @@
    expression a, b;
    @@

    -nir_channels(b, a, 7)
    +nir_trim_vector(b, a, 3)

Plus a fixup for pointless trimming an immediate in RADV and radeonsi.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23352>
 2023-06-06 18:52:25 +00:00
Alyssa Rosenzweig 68eda9456f treewide: Use nir_tex_src_for_ssa 
Via Coccinelle patch:

    @@
    expression a, b, c;
    @@

    -a.src = nir_src_for_ssa(b);
    -a.src_type = c;
    +a = nir_tex_src_for_ssa(c, b);

    @@
    expression a, b, c;
    @@

    -a.src_type = c;
    -a.src = nir_src_for_ssa(b);
    +a = nir_tex_src_for_ssa(c, b);

Plus manual fixups, including...

* a few identity swizzles changed to nir_trim_vector in TTN and prog-to-nir to
  fix the Coccinelle-botched formatting, and similarly a pointless nir_channels
* collapsing a now-pointless temp in vtn

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23352>
 2023-06-06 18:52:25 +00:00
Alyssa Rosenzweig 3863280399 nir: Add and use nir_tex_src_ssa 
This makes texture instructions a lot less annoying to construct, especially in
cases where the deref-based helpers don't work.

I only converted core NIR, not the drivers. Since it was by hand.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23352>
 2023-06-06 18:52:24 +00:00
Marek Olšák 218c00319b amd: remove unused PKT0 definitions 
We never use type 0 packets.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:36 +00:00
Marek Olšák dd5604b94d radeonsi: don't use SET_SH_REG_INDEX if the kernel doesn't use CU reservation 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:36 +00:00
Marek Olšák d98501f5c1 radeonsi: don't use SET_SH_REG_INDEX on gfx7-9 
It was accidentally used with geometry shaders. It might have caused hangs.

Fixes: ccaaf8fe04 - amd: massively simplify how info->spi_cu_en is applied

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:36 +00:00
Marek Olšák 0fecee53cf radeonsi: re-indent gfx10_create_sh_query_result_cs 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:36 +00:00
Marek Olšák acde68b282 radeonsi/ci: add gfx6 failures 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:36 +00:00
Marek Olšák c2b655d788 radeonsi: add a separate cdna_init_compute_preamble_state function 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:36 +00:00
Marek Olšák 7baeb54c2a radeonsi: don't set registers set by CLEAR_STATE in the preamble for gfx10-11 
CLEAR_STATE doesn't clear PA_SC_GENERIC_SCISSOR_* only on some older chips

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:36 +00:00
Marek Olšák 5acff16ce4 radeonsi: add a separate gfx10_init_gfx_preamble_state function 
and set the registers in an order sorted by the offset.

It's less of a mess now.

Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák c4d465a514 radeonsi: add helpers to create and clone a sized pm4 state 
to simplify si_init_cs_preamble_state and it will be used in the following
commits

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák c23597970b radeonsi: don't program COMPUTE_MAX_WAVE_ID (GDS register) on gfx6 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák ead53b62c9 radeonsi: optimize no-op primitive restart index changes thanks to index masking 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák ade70712df radeonsi: rename the msaa_sample_locs state to sample locations 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák d0e141ca73 radeonsi: merge si_emit_msaa_sample_locs with si_emit_sample_locations 
Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák b8fef52f0c radeonsi: move PA_SU_SMALL_PRIM_FILTER_CNTL to the preamble when possible 
PA_SU_SMALL_PRIM_FILTER_CNTL is set in the gfx preamble if the sample loc
bug isn't present. Else, it's set as part of sample locs state.

This is part 3 of simplifying si_emit_msaa_sample_locs.

Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák 547fccaab9 radeonsi: adjust 16x EQAA sample locs to make PA_SU_PRIM_FILTER_CNTL immutable 
and move PA_SU_PRIM_FILTER_CNTL to the gfx preamble.

If sample locations don't use the -8 coordinate, the EXCLUSION can always
be set to 1.

This is part 2 of simplifying si_emit_msaa_sample_locs.

Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák 818381dfbd radeonsi: always set sample locations even for 1x MSAA for simplicity 
This is part 1 of simplifying si_emit_msaa_sample_locs.

Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák f6d861a1c1 radeonsi: move PA_CL_NGG_CNTL emission into rasterizer state 
It's a better place. Edge flags only have effect if polygon mode is
enabled. Changing shaders should no longer roll the context due to line
culling flipping EDGE_FLAG_ENA.

Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák 941e214fe7 radeonsi: reorder and comment tracked registers 
Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák d7802b02c4 radeonsi: split tracked_regs masks into context registers and other registers 
Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák 9cf2e47833 radeonsi: increase SDMA gfx9+ limits 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák 52f94e2b93 radeonsi: decompress DCC for SDMA if we're really going to use SDMA 
change the order of operations

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák d2e6c4d255 radeonsi: unduplicate si_translate_format_to_hw 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák 5f2779f62a radeonsi: completely rewrite how VGT_SHADER_STAGES_EN is set 
Use a state atom with an emit function instead of precomputing up to 256
pm4 states in si_context.

Some register fields are precomputed in si_shader for NGG. Others are set
in si_update_shaders.

Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák cfc9352c25 radeonsi: remove RADEON_FLAG_MALL_NOALLOC due to no use 
and we'll need to use that bit for something else in the future.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák d3f716bdfc radeonsi: add a gfx11 version of si_decompress_textures, add assertions < GFX11 
si_decompress_textures is renamed to gfx6_decompress_textures.
gfx11_decompress_textures is added.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák dc311f3f61 radeonsi: remove a useless depth texture function call in a fast color clear 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák d692d433f2 radeonsi: use nir_lower_alu_to_scalar correctly 
We should use the filter callback that's also used by st/mesa.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák 5066623b79 radeonsi: print shader-db stats with AMD_DEBUG=vs,ps,stats 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák 2bf839f0ae radeonsi/gfx11: extend DB_Z_INFO.NUM_SAMPLES programming to > GFX11 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák 52ca879cdd radeonsi: export non-zero edgeflags for GS and tess 
because edge flags are always enabled when polygon mode is enabled

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák b72a1883e2 radeonsi: remove gl_BackColor VS outputs on demand if color_two_side is disabled 
We just need to set the ps_inputs_read_or_disabled mask correctly.

The VS outputs_written mask should set BFCn instead of COLn, which is why
this removes the is_varying parameter that forced COLn to be set for BFCn.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák a1d938d318 radeonsi: define si_shader_io_get_unique_index() values as SI_UNIQUE_SLOT_* 
for later use

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák ed8250360f amd: add radeon_info* into ac_llvm_context and radv_nir_compiler_options 
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák 192b2c7c31 ac/nir/ngg: always use load_initial_edgeflags_amd, choose the value in drivers 
radeonsi will have a more complicated condition here

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Marek Olšák d6e70334ff ac/surface: fix R32G3B32 image format regression for gfx6-8 
This is a different fix from the one reviewed because that one broke gfx9.

Fixes: ea7c89d1f5 - ac/surface: move determing ADDR_FMT_* into a helper function
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
 2023-06-06 18:01:35 +00:00
Rhys Perry b9c1d74ff4 radv: correctly skip vertex loads with packed formats 
This is supposed to check whether any channels of the element is used, but
skipped_start is always 0 for packed formats.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: a46acdbc3f ("radv: Lower non-dynamic VS inputs in NIR.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9062
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23370>
 2023-06-06 16:59:16 +00:00
Rhys Perry 69e259dcff radv: initialize aco_compiler_options::is_opengl 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Fixes: 8d5cc23c18 ("aco: use gds reg when ordered xfb counter add")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23434>
 2023-06-06 16:09:28 +00:00
Rhys Perry 53383fe8a5 aco: fix ds_sub_gs_reg_rtn validation 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Fixes: 8d5cc23c18 ("aco: use gds reg when ordered xfb counter add")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23434>
 2023-06-06 16:09:28 +00:00
Charmaine Lee e2927dd5e7 mesa/main: fix distance attenuation calculation in ffvertex 
The dist parameter to calculate_light_attenuation() is the
reciprocal of ||VP|| used in the distance attenuation formula (2.4).
So get its reciprocal first before applying it to the distance attenuation
formula.

This fixes a lighting issue in Knights of the Old Republic.

Fixes: c5b3d488f9 ("mesa/main: make ffvertex output nir")

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collaborar.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23404>
 2023-06-06 15:15:55 +00:00
Lionel Landwerlin 049c791a63 intel/fs: fix pull-constant-load prior to gfx7 
In ad9bc1ffb5 ("intel/fs: enable UBO accesses through bindless heap")
we added a new source, we need to fixup the source index for the
generator.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ad9bc1ffb5 ("intel/fs: enable UBO accesses through bindless heap")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23405>
 2023-06-06 14:47:41 +00:00