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radeonsi: split tracked_regs masks into context registers and other registers

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Acked-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
This commit is contained in:
Marek Olšák
2023-05-12 23:49:13 -04:00
committed by Marge Bot
parent 9cf2e47833
commit d7802b02c4
3 changed files with 128 additions and 119 deletions
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src/gallium/drivers/radeonsi/si_build_pm4.h
+52 -52
View File
@@ -157,11 +157,11 @@
/* Emit PKT3_SET_CONTEXT_REG if the register value is different. */
#define radeon_opt_set_context_reg(sctx, offset, reg, val) do { \
unsigned __value = val; \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
sctx->tracked_regs.reg_value[reg] != __value) { \
if (((sctx->tracked_regs.context_reg_saved_mask >> (reg)) & 0x1) != 0x1 || \
sctx->tracked_regs.context_reg_value[reg] != __value) { \
radeon_set_context_reg(offset, __value); \
sctx->tracked_regs.reg_saved |= 0x1ull << (reg); \
sctx->tracked_regs.reg_value[reg] = __value; \
sctx->tracked_regs.context_reg_saved_mask |= 0x1ull << (reg); \
sctx->tracked_regs.context_reg_value[reg] = __value; \
} \
} while (0)
@@ -173,15 +173,15 @@
*/
#define radeon_opt_set_context_reg2(sctx, offset, reg, val1, val2) do { \
unsigned __value1 = (val1), __value2 = (val2); \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x3) != 0x3 || \
sctx->tracked_regs.reg_value[reg] != __value1 || \
sctx->tracked_regs.reg_value[(reg) + 1] != __value2) { \
if (((sctx->tracked_regs.context_reg_saved_mask >> (reg)) & 0x3) != 0x3 || \
sctx->tracked_regs.context_reg_value[reg] != __value1 || \
sctx->tracked_regs.context_reg_value[(reg) + 1] != __value2) { \
radeon_set_context_reg_seq(offset, 2); \
radeon_emit(__value1); \
radeon_emit(__value2); \
sctx->tracked_regs.reg_value[reg] = __value1; \
sctx->tracked_regs.reg_value[(reg) + 1] = __value2; \
sctx->tracked_regs.reg_saved |= 0x3ull << (reg); \
sctx->tracked_regs.context_reg_value[reg] = __value1; \
sctx->tracked_regs.context_reg_value[(reg) + 1] = __value2; \
sctx->tracked_regs.context_reg_saved_mask |= 0x3ull << (reg); \
} \
} while (0)
@@ -190,18 +190,18 @@
*/
#define radeon_opt_set_context_reg3(sctx, offset, reg, val1, val2, val3) do { \
unsigned __value1 = (val1), __value2 = (val2), __value3 = (val3); \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x7) != 0x7 || \
sctx->tracked_regs.reg_value[reg] != __value1 || \
sctx->tracked_regs.reg_value[(reg) + 1] != __value2 || \
sctx->tracked_regs.reg_value[(reg) + 2] != __value3) { \
if (((sctx->tracked_regs.context_reg_saved_mask >> (reg)) & 0x7) != 0x7 || \
sctx->tracked_regs.context_reg_value[reg] != __value1 || \
sctx->tracked_regs.context_reg_value[(reg) + 1] != __value2 || \
sctx->tracked_regs.context_reg_value[(reg) + 2] != __value3) { \
radeon_set_context_reg_seq(offset, 3); \
radeon_emit(__value1); \
radeon_emit(__value2); \
radeon_emit(__value3); \
sctx->tracked_regs.reg_value[reg] = __value1; \
sctx->tracked_regs.reg_value[(reg) + 1] = __value2; \
sctx->tracked_regs.reg_value[(reg) + 2] = __value3; \
sctx->tracked_regs.reg_saved |= 0x7ull << (reg); \
sctx->tracked_regs.context_reg_value[reg] = __value1; \
sctx->tracked_regs.context_reg_value[(reg) + 1] = __value2; \
sctx->tracked_regs.context_reg_value[(reg) + 2] = __value3; \
sctx->tracked_regs.context_reg_saved_mask |= 0x7ull << (reg); \
} \
} while (0)
@@ -210,21 +210,21 @@
*/
#define radeon_opt_set_context_reg4(sctx, offset, reg, val1, val2, val3, val4) do { \
unsigned __value1 = (val1), __value2 = (val2), __value3 = (val3), __value4 = (val4); \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0xf) != 0xf || \
sctx->tracked_regs.reg_value[reg] != __value1 || \
sctx->tracked_regs.reg_value[(reg) + 1] != __value2 || \
sctx->tracked_regs.reg_value[(reg) + 2] != __value3 || \
sctx->tracked_regs.reg_value[(reg) + 3] != __value4) { \
if (((sctx->tracked_regs.context_reg_saved_mask >> (reg)) & 0xf) != 0xf || \
sctx->tracked_regs.context_reg_value[reg] != __value1 || \
sctx->tracked_regs.context_reg_value[(reg) + 1] != __value2 || \
sctx->tracked_regs.context_reg_value[(reg) + 2] != __value3 || \
sctx->tracked_regs.context_reg_value[(reg) + 3] != __value4) { \
radeon_set_context_reg_seq(offset, 4); \
radeon_emit(__value1); \
radeon_emit(__value2); \
radeon_emit(__value3); \
radeon_emit(__value4); \
sctx->tracked_regs.reg_value[reg] = __value1; \
sctx->tracked_regs.reg_value[(reg) + 1] = __value2; \
sctx->tracked_regs.reg_value[(reg) + 2] = __value3; \
sctx->tracked_regs.reg_value[(reg) + 3] = __value4; \
sctx->tracked_regs.reg_saved |= 0xfull << (reg); \
sctx->tracked_regs.context_reg_value[reg] = __value1; \
sctx->tracked_regs.context_reg_value[(reg) + 1] = __value2; \
sctx->tracked_regs.context_reg_value[(reg) + 2] = __value3; \
sctx->tracked_regs.context_reg_value[(reg) + 3] = __value4; \
sctx->tracked_regs.context_reg_saved_mask |= 0xfull << (reg); \
} \
} while (0)
@@ -233,24 +233,24 @@
*/
#define radeon_opt_set_context_reg5(sctx, offset, reg, val0, val1, val2, val3, val4) do { \
unsigned __value0 = (val0), __value1 = (val1), __value2 = (val2), __value3 = (val3), __value4 = (val4); \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1f) != 0x1f || \
sctx->tracked_regs.reg_value[(reg) + 0] != __value0 || \
sctx->tracked_regs.reg_value[(reg) + 1] != __value1 || \
sctx->tracked_regs.reg_value[(reg) + 2] != __value2 || \
sctx->tracked_regs.reg_value[(reg) + 3] != __value3 || \
sctx->tracked_regs.reg_value[(reg) + 4] != __value4) { \
if (((sctx->tracked_regs.context_reg_saved_mask >> (reg)) & 0x1f) != 0x1f || \
sctx->tracked_regs.context_reg_value[(reg) + 0] != __value0 || \
sctx->tracked_regs.context_reg_value[(reg) + 1] != __value1 || \
sctx->tracked_regs.context_reg_value[(reg) + 2] != __value2 || \
sctx->tracked_regs.context_reg_value[(reg) + 3] != __value3 || \
sctx->tracked_regs.context_reg_value[(reg) + 4] != __value4) { \
radeon_set_context_reg_seq(offset, 5); \
radeon_emit(__value0); \
radeon_emit(__value1); \
radeon_emit(__value2); \
radeon_emit(__value3); \
radeon_emit(__value4); \
sctx->tracked_regs.reg_value[(reg) + 0] = __value0; \
sctx->tracked_regs.reg_value[(reg) + 1] = __value1; \
sctx->tracked_regs.reg_value[(reg) + 2] = __value2; \
sctx->tracked_regs.reg_value[(reg) + 3] = __value3; \
sctx->tracked_regs.reg_value[(reg) + 4] = __value4; \
sctx->tracked_regs.reg_saved |= 0x1full << (reg); \
sctx->tracked_regs.context_reg_value[(reg) + 0] = __value0; \
sctx->tracked_regs.context_reg_value[(reg) + 1] = __value1; \
sctx->tracked_regs.context_reg_value[(reg) + 2] = __value2; \
sctx->tracked_regs.context_reg_value[(reg) + 3] = __value3; \
sctx->tracked_regs.context_reg_value[(reg) + 4] = __value4; \
sctx->tracked_regs.context_reg_saved_mask |= 0x1full << (reg); \
} \
} while (0)
@@ -267,31 +267,31 @@
#define radeon_opt_set_sh_reg(sctx, offset, reg, val) do { \
unsigned __value = val; \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
sctx->tracked_regs.reg_value[reg] != __value) { \
if (((sctx->tracked_regs.other_reg_saved_mask >> (reg)) & 0x1) != 0x1 || \
sctx->tracked_regs.other_reg_value[reg] != __value) { \
radeon_set_sh_reg(offset, __value); \
sctx->tracked_regs.reg_saved |= BITFIELD64_BIT(reg); \
sctx->tracked_regs.reg_value[reg] = __value; \
sctx->tracked_regs.other_reg_saved_mask |= BITFIELD64_BIT(reg); \
sctx->tracked_regs.other_reg_value[reg] = __value; \
} \
} while (0)
#define radeon_opt_set_sh_reg_idx3(sctx, offset, reg, val) do { \
unsigned __value = val; \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
sctx->tracked_regs.reg_value[reg] != __value) { \
if (((sctx->tracked_regs.other_reg_saved_mask >> (reg)) & 0x1) != 0x1 || \
sctx->tracked_regs.other_reg_value[reg] != __value) { \
radeon_set_sh_reg_idx3(sctx, offset, __value); \
sctx->tracked_regs.reg_saved |= BITFIELD64_BIT(reg); \
sctx->tracked_regs.reg_value[reg] = __value; \
sctx->tracked_regs.other_reg_saved_mask |= BITFIELD64_BIT(reg); \
sctx->tracked_regs.other_reg_value[reg] = __value; \
} \
} while (0)
#define radeon_opt_set_uconfig_reg(sctx, offset, reg, val) do { \
unsigned __value = val; \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
sctx->tracked_regs.reg_value[reg] != __value) { \
if (((sctx->tracked_regs.other_reg_saved_mask >> (reg)) & 0x1) != 0x1 || \
sctx->tracked_regs.other_reg_value[reg] != __value) { \
radeon_set_uconfig_reg(offset, __value); \
sctx->tracked_regs.reg_saved |= 0x1ull << (reg); \
sctx->tracked_regs.reg_value[reg] = __value; \
sctx->tracked_regs.other_reg_saved_mask |= 0x1ull << (reg); \
sctx->tracked_regs.other_reg_value[reg] = __value; \
} \
} while (0)
src/gallium/drivers/radeonsi/si_gfx_cs.c
+65 -63
View File
@@ -231,71 +231,71 @@ void si_allocate_gds(struct si_context *sctx)
void si_set_tracked_regs_to_clear_state(struct si_context *ctx)
{
STATIC_ASSERT(SI_NUM_TRACKED_REGS <= sizeof(ctx->tracked_regs.reg_saved) * 8);
STATIC_ASSERT(SI_NUM_TRACKED_CONTEXT_REGS <= sizeof(ctx->tracked_regs.context_reg_saved_mask) * 8);
ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_CONTROL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_DB_COUNT_CONTROL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_CB_TARGET_MASK] = 0xffffffff;
ctx->tracked_regs.reg_value[SI_TRACKED_CB_DCC_CONTROL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SX_PS_DOWNCONVERT] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_EPSILON] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SX_BLEND_OPT_CONTROL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_CNTL] = 0x00001000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_AA_CONFIG] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_DB_EQAA] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_MODE_CNTL_1] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x00000003;
ctx->tracked_regs.reg_value[SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ] = 0x3f800000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ] = 0x3f800000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ] = 0x3f800000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ] = 0x3f800000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x00000005;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE] = 0xffff;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_STIPPLE] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_3] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_ITEMSIZE] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_VERT_OUT] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_INSTANCE_CNT] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_ONCHIP_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_MODE] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_REUSE_OFF] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_GE_NGG_SUBGRP_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_IDX_FORMAT] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_VTE_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_CL_NGG_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ENA] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_BARYC_CNTL] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_IN_CONTROL] = 0x00000002;
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_CB_SHADER_MASK] = 0xffffffff;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL] = 0x0000001e; /* From GFX8 */
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_SHADER_STAGES_EN] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_RENDER_CONTROL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_COUNT_CONTROL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_CB_TARGET_MASK] = 0xffffffff;
ctx->tracked_regs.context_reg_value[SI_TRACKED_CB_DCC_CONTROL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_SX_PS_DOWNCONVERT] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_SX_BLEND_OPT_EPSILON] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_SX_BLEND_OPT_CONTROL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_LINE_CNTL] = 0x00001000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_AA_CONFIG] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_EQAA] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_MODE_CNTL_1] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_PRIM_FILTER_CNTL] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_VS_OUT_CNTL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_CLIP_CNTL] = 0x00090000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_BINNER_CNTL_0] = 0x00000003;
ctx->tracked_regs.context_reg_value[SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ] = 0x3f800000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ] = 0x3f800000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ] = 0x3f800000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ] = 0x3f800000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x00000005;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE] = 0xffff;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_SC_LINE_STIPPLE] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_3] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_ITEMSIZE] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_MAX_VERT_OUT] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_INSTANCE_CNT] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_ONCHIP_CNTL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_MODE] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_REUSE_OFF] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_GE_NGG_SUBGRP_CNTL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_IDX_FORMAT] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_POS_FORMAT] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_VTE_CNTL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_PA_CL_NGG_CNTL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_PS_INPUT_ENA] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_BARYC_CNTL] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_PS_IN_CONTROL] = 0x00000002;
ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_CB_SHADER_MASK] = 0xffffffff;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_TF_PARAM] = 0x00000000;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL] = 0x0000001e; /* From GFX8 */
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_SHADER_STAGES_EN] = 0;
/* Set all cleared context registers to saved. */
ctx->tracked_regs.reg_saved = BITFIELD64_MASK(SI_TRACKED_GE_PC_ALLOC);
ctx->tracked_regs.context_reg_saved_mask = BITFIELD64_MASK(SI_NUM_TRACKED_CONTEXT_REGS);
if (ctx->gfx_level >= GFX11)
ctx->last_gs_out_prim = -1; /* uconfig register, unknown value */
@@ -505,12 +505,14 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
si_set_tracked_regs_to_clear_state(ctx);
} else {
/* Set all register values to unknown. */
ctx->tracked_regs.reg_saved = 0;
ctx->tracked_regs.context_reg_saved_mask = 0;
ctx->last_gs_out_prim = -1; /* unknown */
}
/* 0xffffffff is an impossible value to register SPI_PS_INPUT_CNTL_n */
memset(ctx->tracked_regs.spi_ps_input_cntl, 0xff, sizeof(uint32_t) * 32);
ctx->tracked_regs.other_reg_saved_mask = 0; /* unknown values */
}
/* Invalidate various draw states so that they are emitted before
src/gallium/drivers/radeonsi/si_state.h
+11 -4
View File
@@ -230,7 +230,7 @@ struct si_shader_data {
};
/* The list of registers whose emitted values are remembered by si_context. */
enum si_tracked_reg
enum si_tracked_context_reg
{
SI_TRACKED_DB_RENDER_CONTROL, /* 2 consecutive registers */
SI_TRACKED_DB_COUNT_CONTROL,
@@ -316,18 +316,25 @@ enum si_tracked_reg
SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
SI_TRACKED_VGT_SHADER_STAGES_EN,
SI_NUM_TRACKED_CONTEXT_REGS,
};
enum si_tracked_other_reg {
/* Non-context registers: */
SI_TRACKED_GE_PC_ALLOC,
SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
SI_NUM_TRACKED_REGS,
SI_NUM_TRACKED_OTHER_REGS,
};
struct si_tracked_regs {
uint64_t reg_saved;
uint32_t reg_value[SI_NUM_TRACKED_REGS];
uint64_t context_reg_saved_mask;
uint32_t context_reg_value[SI_NUM_TRACKED_CONTEXT_REGS];
uint32_t spi_ps_input_cntl[32];
uint32_t other_reg_saved_mask;
uint32_t other_reg_value[SI_NUM_TRACKED_OTHER_REGS];
};
/* Private read-write buffer slots. */