radeonsi: increase SDMA gfx9+ limits
Reviewed-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
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@@ -52,9 +52,11 @@ static unsigned encode_legacy_tile_info(struct si_context *sctx, struct si_textu
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(G_009910_PIPE_CONFIG(tile_mode) << 26);
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}
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static
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bool si_sdma_v4_v5_copy_texture(struct si_context *sctx, struct si_texture *sdst, struct si_texture *ssrc, bool is_v5)
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static bool si_sdma_v4_v5_copy_texture(struct si_context *sctx, struct si_texture *sdst,
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struct si_texture *ssrc)
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{
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bool is_v5 = sctx->gfx_level >= GFX10;
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bool is_v5_2 = sctx->gfx_level >= GFX10_3;
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unsigned bpp = sdst->surface.bpe;
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uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.gfx9.surf_offset;
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uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.gfx9.surf_offset;
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@@ -72,7 +74,7 @@ bool si_sdma_v4_v5_copy_texture(struct si_context *sctx, struct si_texture *sdst
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uint64_t bytes = (uint64_t)src_pitch * copy_height * bpp;
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if (!(bytes < (1u << 22)))
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if (!(bytes <= (1u << (is_v5_2 ? 30 : 22))))
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return false;
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src_address += ssrc->surface.u.gfx9.offset[0];
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@@ -110,9 +112,9 @@ bool si_sdma_v4_v5_copy_texture(struct si_context *sctx, struct si_texture *sdst
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linear_address += linear->surface.u.gfx9.offset[0];
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/* Check if everything fits into the bitfields */
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if (!(tiled_width < (1 << 14) && tiled_height < (1 << 14) &&
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linear_pitch < (1 << 14) && linear_slice_pitch < (1 << 28) &&
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copy_width < (1 << 14) && copy_height < (1 << 14)))
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if (!(tiled_width <= (1 << 14) && tiled_height <= (1 << 14) &&
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linear_pitch <= (1 << 14) && linear_slice_pitch <= (1 << 28) &&
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copy_width <= (1 << 14) && copy_height <= (1 << 14)))
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return false;
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radeon_begin(cs);
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@@ -401,7 +403,7 @@ bool si_sdma_copy_image(struct si_context *sctx, struct si_texture *dst, struct
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case GFX10:
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case GFX10_3:
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case GFX11:
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if (!si_sdma_v4_v5_copy_texture(sctx, dst, src, sctx->gfx_level >= GFX10))
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if (!si_sdma_v4_v5_copy_texture(sctx, dst, src))
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return false;
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break;
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default:
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