radeonsi: don't use SET_SH_REG_INDEX if the kernel doesn't use CU reservation

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>

src/amd/common/ac_gpu_info.c

@@ -965,6 +965,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
    info->mid_command_buffer_preemption_enabled = device_info.ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
    info->has_tmz_support = has_tmz_support(dev, info, device_info.ids_flags);
    info->kernel_has_modifiers = has_modifiers(fd);
+   info->uses_kernel_cu_mask = false; /* Not implemented in the kernel. */
    info->has_graphics = info->ip[AMD_IP_GFX].num_queues > 0;
 
    info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
@@ -1755,6 +1756,8 @@ void ac_print_gpu_info(const struct radeon_info *info, FILE *f)
                  info->max_submitted_ibs[i]);
       }
    }
+   fprintf(f, "    kernel_has_modifiers = %u\n", info->kernel_has_modifiers);
+   fprintf(f, "    uses_kernel_cu_mask = %u\n", info->uses_kernel_cu_mask);
 
    fprintf(f, "Shader core info:\n");
    for (unsigned i = 0; i < info->max_se; i++) {

src/amd/common/ac_gpu_info.h

@@ -210,6 +210,21 @@ struct radeon_info {
    bool has_tmz_support;
    bool kernel_has_modifiers;
 
+   /* If the kernel driver uses CU reservation for high priority compute on gfx10+, it programs
+    * a global CU mask in the hw that is AND'ed with CU_EN register fields set by userspace.
+    * The packet that does the AND'ing is SET_SH_REG_INDEX(index = 3). If you don't use
+    * SET_SH_REG_INDEX, the global CU mask will not be applied.
+    *
+    * If uses_kernel_cu_mask is true, use SET_SH_REG_INDEX.
+    *
+    * If uses_kernel_cu_mask is false, SET_SH_REG_INDEX shouldn't be used because it only
+    * increases CP overhead and doesn't have any other effect.
+    *
+    * The alternative to this is to set the AMD_CU_MASK environment variable that has the same
+    * effect on radeonsi and RADV and doesn't need SET_SH_REG_INDEX.
+    */
+   bool uses_kernel_cu_mask;
+
    /* Shader cores. */
    uint16_t cu_mask[AMD_MAX_SE][AMD_MAX_SA_PER_SE];
    uint32_t r600_max_quad_pipes; /* wave size / 16 */

src/gallium/drivers/radeonsi/si_build_pm4.h

@@ -110,7 +110,8 @@
 #define radeon_set_sh_reg_idx3_seq(sctx, reg, num) do { \
    SI_CHECK_SHADOWED_REGS(reg, num); \
    assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
-   if ((sctx)->gfx_level >= GFX10) { \
+   if ((sctx)->screen->info.uses_kernel_cu_mask) { \
+      assert((sctx)->gfx_level >= GFX10); \
       radeon_emit(PKT3(PKT3_SET_SH_REG_INDEX, num, 0)); \
       radeon_emit((((reg) - SI_SH_REG_OFFSET) >> 2) | (3 << 28)); \
    } else { \

src/gallium/drivers/radeonsi/si_pm4.c

@@ -92,10 +92,12 @@ void si_pm4_set_reg_idx3(struct si_screen *sscreen, struct si_pm4_state *state,
 {
    SI_CHECK_SHADOWED_REGS(reg, 1);
 
-   if (sscreen->info.gfx_level >= GFX10)
+   if (sscreen->info.uses_kernel_cu_mask) {
+      assert(sscreen->info.gfx_level >= GFX10);
       si_pm4_set_reg_custom(state, reg - SI_SH_REG_OFFSET, val, PKT3_SET_SH_REG_INDEX, 3);
-   else
+   } else {
       si_pm4_set_reg_custom(state, reg - SI_SH_REG_OFFSET, val, PKT3_SET_SH_REG, 0);
+   }
 }
 
 void si_pm4_set_reg_va(struct si_pm4_state *state, unsigned reg, uint32_t val)