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Author SHA1 Message Date
Kenneth Graunke
d525d2456a brw: Calculate tessellation URB offsets when lowering to URB intrinsics 
This now lowers IO intrinsics to URB intrinsics in a single step,
rather than modifying IO intrinsics to have non-standard meanings
temporarily.  We are able to drop one "no_validate" flag.

For example, remap_patch_urb_offsets had added (vertex * stride) to
(offset) for per-vertex IO intrinsics, but left them as per-vertex
intrinsics.  Now we just have an urb_offset() function to calculate
that when doing the lowering.

This also provides a central location for calculating URB offsets,
which we should be able to extend for other uses (per-view lowering,
mesh per-primitive lowering) in future patches.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38918>
 2025-12-16 00:58:34 +00:00
Kenneth Graunke
b02a01c636 intel: Replace signed char with int8_t 
Let's use modern stdint types.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38918>
 2025-12-16 00:58:32 +00:00
Dylan Baker
ca96f8517c iris: remove uses of pipe_surface as a pointer 
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36690>
 2025-12-15 14:38:40 -08:00
Mauro Rossi
e8134e6eaf radv/rt: Fix gnu-empty-initializer error 
Fixes the following building error happening with clang:

FAILED: src/amd/vulkan/libvulkan_radeon.so.p/nir_radv_nir_rt_traversal_shader.c.o
...
../src/amd/vulkan/nir/radv_nir_rt_traversal_shader.c:1159:49: error: use of GNU empty initializer extension [-Werror,-Wgnu-empty-initializer]
   struct radv_nir_rt_traversal_params params = {};
                                                ^
1 error generated.

Fixes: f692ac76 ("radv/rt: Use traversal vars for object origin/direction in ahit/isec")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38954>
 2025-12-15 22:27:29 +01:00
Timur Kristóf
0324700c03 radv: Use zero-filled BO for GFX6 and GFX10 null index buffer bug 
GFX10 hangs when drawing from a 0-sized index buffer.
GFX6 has a HW bug when the index buffer	address is 0.

Looking at VK CTS runs, GFX6 still triggers VM faults despite the
current mitigation, and it also tries to access memory when the
index buffer is zero sized. So it looks like GFX6 and GFX10
really have the same bug.

Let's share the mitigation between the two.
Use a zero-filled BO instead of the upload buffer.
This fixes VM faults on GFX6, and should speed up GFX10 a bit.

Note that the zero-filled BO is also going to be used for
other bug mitigations on GFX6-7.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38958>
 2025-12-15 21:03:19 +00:00
Timur Kristóf
f001515c87 aco: Use only VGPR offset on buffer atomics on GFX6-7 
SGPR offset is not included in the bounds check
according to the ISA documentation of GFX6-7 and
indeed it can trigger VM faults on OOB access.

Note that ACO already doesn't use the SGPR offset
on GFX6-7 for buffer loads and stores. This commit
just does the same for buffer atomics.

This commit mitigates a ton of VM faults that are exposed by:
24e75fea4b

Fossil DB stats on Hawaii (GFX7):

Totals from 148 (0.24% of 61818) affected shaders:
Instrs: 324004 -> 327352 (+1.03%)
CodeSize: 1556468 -> 1514100 (-2.72%); split: -2.74%, +0.02%
Latency: 1271480 -> 1276894 (+0.43%)
InvThroughput: 396850 -> 397740 (+0.22%)
VClause: 6861 -> 6858 (-0.04%)
Copies: 34083 -> 37430 (+9.82%)
PreVGPRs: 5705 -> 5706 (+0.02%)
VALU: 147529 -> 150898 (+2.28%)
SALU: 98194 -> 98172 (-0.02%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38958>
 2025-12-15 21:03:19 +00:00
Ian Forbes
42e797b139 svga: Report "VRAM" more accurately 
While the concept of "VRAM" is somewhat nebulous on SVGA devices this is
the value above which some performance degradation is likely to occur.

Signed-off-by: Ian Forbes <ian.forbes@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38818>
 2025-12-15 20:45:18 +00:00
Lionel Landwerlin
94d2ec975d anv: disable crast on SKL 
SKL is failing the following tests (maybe more) :

dEQP-VK.rasterization.conservative.overestimate.samples_1.triangles.degenerate.0_00
dEQP-VK.rasterization.conservative.overestimate.samples_16.triangles.degenerate.max
dEQP-VK.rasterization.conservative.overestimate.samples_2.triangles.degenerate.max
dEQP-VK.rasterization.conservative.overestimate.samples_2.triangles.degenerate.min
dEQP-VK.rasterization.conservative.overestimate.samples_4.triangles.degenerate.0_00
dEQP-VK.rasterization.conservative.overestimate.samples_8.triangles.degenerate.max
dEQP-VK.rasterization.conservative.overestimate.samples_8.triangles.degenerate.min

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38951>
 2025-12-15 20:15:03 +00:00
Benjamin Cheng
59f821218c radv/video: Move probability table filling to bind 
We should not manipulate the session buffers at command recording time.
It shouldn't cause any problems as these initialized probability tables
are not modified by firmware, but moving these to bind time should be
safer and also faster if an application frequently RESETs.

Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38926>
 2025-12-15 18:49:28 +00:00
Aaron Ruby
3bddd2eaed Revert "device-select-layer: Implement VkNegotiateLayerInterface::pfnGetDeviceProcAddr" 
This reverts commit b17896f693

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38953>
 2025-12-15 16:46:13 +00:00
José Roberto de Souza
518705a4fe intel/brw: Split to a function the code that calculate sampler channels that should be written 
This block of code will be re-used in a future patch, also it reduces a bit the
size and complexity of lower_sampler_logical_send().
No changes in behavior intended here.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38792>
 2025-12-15 06:57:15 -08:00
Nanley Chery
188193cbf2 iris: Add comments from Bspec fast-clear preamble page 
Copy and paste from anv.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38928>
 2025-12-15 12:42:57 +00:00
Nanley Chery
18e67d853f iris: Fix pipe control around fast-clears 
Use the right pipe control helper function so that texture invalidates
occur after the end-of-pipe sync rather than during.

Fixes: 23658920d1 ("anv,iris: Skip tex invalidate for clear conversion")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12550
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38928>
 2025-12-15 12:42:57 +00:00
Georg Lehmann
a2b70ce4ec aco/isel: remove uniform reduce/scan optimization 
This is now done in NIR, with the exception of exclusive min/max/and/or scans.
But those are not really useful, and if we ever come across them we can
optimize them in NIR using write_invocation_amd.

No Foz-DB changes on Navi21.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38902>
 2025-12-15 12:22:32 +00:00
Georg Lehmann
81245e262f radeonsi: use nir_opt_uniform_subgroup 
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38902>
 2025-12-15 12:22:32 +00:00
Georg Lehmann
ec81337d8d radv: use nir_opt_uniform_subgroup 
Foz-DB Navi21:
Totals from 665 (0.68% of 97581) affected shaders:
MaxWaves: 12856 -> 12822 (-0.26%)
Instrs: 2073376 -> 2068645 (-0.23%); split: -0.23%, +0.00%
CodeSize: 11116904 -> 11098376 (-0.17%); split: -0.18%, +0.01%
VGPRs: 39584 -> 39568 (-0.04%); split: -0.20%, +0.16%
SpillSGPRs: 160 -> 155 (-3.12%)
SpillVGPRs: 2995 -> 2968 (-0.90%)
Latency: 15432093 -> 15503462 (+0.46%); split: -0.13%, +0.59%
InvThroughput: 3344411 -> 3351185 (+0.20%); split: -0.08%, +0.28%
VClause: 50278 -> 50225 (-0.11%); split: -0.15%, +0.04%
SClause: 57537 -> 57505 (-0.06%); split: -0.18%, +0.13%
Copies: 189642 -> 188175 (-0.77%); split: -0.86%, +0.08%
Branches: 68800 -> 68502 (-0.43%); split: -0.45%, +0.02%
PreSGPRs: 37646 -> 37068 (-1.54%)
PreVGPRs: 35891 -> 35943 (+0.14%)
VALU: 1386943 -> 1385881 (-0.08%); split: -0.09%, +0.01%
SALU: 287322 -> 284165 (-1.10%); split: -1.11%, +0.01%
VMEM: 90874 -> 90820 (-0.06%)

Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38902>
 2025-12-15 12:22:32 +00:00
Jose Maria Casanova Crespo
f57add1d14 v3dv: Enable TFU blits with raster destinations on 7.1 HW (RPi5) 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38910>
 2025-12-15 11:57:51 +00:00
Jose Maria Casanova Crespo
19580dfae1 v3d: Enable TFU blits with raster destinations on 7.1 HW (RPi5) 
We take advantage or fixing a typo in TFU_IOC formats defines
when adding the TFU_IOC_RASTER FORMAT.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38910>
 2025-12-15 11:57:51 +00:00
Jose Maria Casanova Crespo
40339ada9c broadcom: Drop use of nir_lower_wrmasks 
v3d_nir_lower_load_store_bitsize that uses nir_lower_mem_access_bit_sizes
already ensures that any writemask on store has consecutive bits set.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38921>
 2025-12-15 11:34:27 +00:00
Valentine Burley
b1de4249f7 lavapipe/ci: Add a nightly ASAN job 
This is a longer, nightly variant of lavapipe-vkcts-asan that runs
1/40 of dEQP instead of 1/1000.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14042
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38870>
 2025-12-15 11:19:21 +00:00
Karmjit Mahil
cfd10a729d gallium: Fix gnu-empty-initalizer error 
Addresses:
```
../src/gallium/auxiliary/hud/hud_context.c:498:42: error: use of GNU
empty initializer extension [-Werror,-Wgnu-empty-initializer]
   struct pipe_resource *releasebuf[3] = {};
                                         ^

../src/gallium/auxiliary/postprocess/pp_mlaa.c:76:42: error: use of GNU
empty initializer extension [-Werror,-Wgnu-empty-initializer]
   struct pipe_resource *releasebuf[2] = {};
                                         ^
```

Fixes: 51605bfac2 ("gallium: Make upload_cb0 return a releasebuf")
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38920>
 2025-12-15 09:35:25 +00:00
Mary Guillemard
86d190e158 nvk: Use rendering state attachment count when setting SET_CT_SELECT 
In case vk_color_attachment_location_state is in its default state, we
would end up with an identity mapping for color_map resulting in 8 RTs
being selected instead of what is really required.

This now use the rendering state attachment count to properly emit
SET_CT_SELECT.

Found while debugging MRT on
"dEQP-VK.shader_object.rendering.color_attachment_count_1.extra_attachment_after_1.none.none.same_color_formats.after.none.r16g16_sint_d32_sfloat_s8_uint"
and while comparing with the proprietary driver.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Fixes: 84de6c12b2 ("nvk: Emit SET_CT_SELECT based on the dynamic color location map")
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38946>
 2025-12-15 09:03:42 +00:00
Lionel Landwerlin
e241e30986 anv: add a no-resource-barrier debug flag 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:42 +00:00
Lionel Landwerlin
5f58ac7b11 anv: implement WA_18039014283 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:42 +00:00
Lionel Landwerlin
15174b185b anv: instrument resource barriers instruction in u_trace 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:42 +00:00
Lionel Landwerlin
3520abf8a3 anv: use RESOURCE_BARRIER for event waiting when possible 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:41 +00:00
Lionel Landwerlin
5f9ece0b83 anv: implement Wa_18037648410 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:41 +00:00
Rohan Garg
24e9afb0b7 anv: implement resource barrier emissions 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:40 +00:00
Lionel Landwerlin
e5fc567f49 anv: introduce an new virtual pipecontrol flag for BTI change 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:40 +00:00
Lionel Landwerlin
682f907228 intel: rename DCFlushEnable to ForceDeviceCoherency 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:39 +00:00
Rohan Garg
e55a7bc83a anv: program STATE_COMPUTE_MODE to flush the L1 cache 
This is required for upcoming resource barrier work to implement HDC
flush's.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:39 +00:00
Lionel Landwerlin
47bc9da064 anv: use anv_add_pending_pipe_bits for event reset 
Nicer tracking with INTEL_DEBUG=pc

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:39 +00:00
Lionel Landwerlin
8834ef8bcd anv: use flushing PIPE_CONTROL for event signaling 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:38 +00:00
Lionel Landwerlin
a06b0213c8 anv: switch events to use 0/!0 values for unsignaled/signaled 
RESOURCE_BARRIER cannot write a particular value, just a HW generated
ID.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:38 +00:00
Lionel Landwerlin
5b0c2339d5 anv: use the blitter/video barrier helper for event signalling 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:37 +00:00
Lionel Landwerlin
5dd6f0d0ef anv: store event creation flags 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:37 +00:00
Lionel Landwerlin
72ee520b36 anv: remove unused event field 
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:36 +00:00
Lionel Landwerlin
23be634934 anv: disable deferred bits on Gfx20+ 
Gfx20+ doesn't do PIPELINE_SELECT, the assumption is that we can now
do any PIPE_CONTROL we want regardless of the pipeline mode.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:36 +00:00
Lionel Landwerlin
be5f5f659f anv: consider CS coherent with L3 on Xe2+ 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:35 +00:00
Lionel Landwerlin
503355c7f8 anv: update pipeline barriers for Xe2+ 
We experimentally found that some fixed functions have apparently be
hooked up to the L3. So we can drop a some flushing.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:34 +00:00
Lionel Landwerlin
15524de710 anv: remove pb-stalls from various locations 
Now that we track the stages, it's not required to add those bits
anymore.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:34 +00:00
Lionel Landwerlin
86dceded22 anv: move cs/pb-stall detection to flushing function 
Now that we have the stages accumulated, we can delay this at flushing
time.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:33 +00:00
Lionel Landwerlin
f2c571fabf anv: add tracking of involved stages in pipe flushes 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:32 +00:00
Lionel Landwerlin
4e8a25cf6f anv: remove use of emit_apply_pipe_flushes() in various helpers 
For a bunch of workarounds and special cases we want PIPE_CONTROL not
RESOURCE_BARRIER. We want emit_apply_pipe_flushes() to be mostly for
application barriers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:31 +00:00
Lionel Landwerlin
d37a888a9b anv: remove unused gpu_memcpy function 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
 2025-12-15 08:25:31 +00:00
Mel Henning
01cf905c71 nak: Set variable_latency=0 for !needs_scoreboard 
This simplifies usage of estimate_variable_latency a little in that we
can just use it directly in our max() expressions instead of guarding it
with an if.

Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38939>
 2025-12-13 16:29:18 +00:00
Mel Henning
b4bac84d3b nak: Add a Dst::file() helper function 
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38939>
 2025-12-13 16:29:18 +00:00
Mel Henning
f5f89407f6 nak: Handle CS2R latencies in SSA form 
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38939>
 2025-12-13 16:29:18 +00:00
Georg Lehmann
fee87679bf radv/nir: fix front_face_fsign opt 
If front facing primitives are culled, there are only back facing fragments left.

Fixes: 0fe8250bf4 ("radv: optimize known front_face_fsign too")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38937>
 2025-12-13 10:22:21 +01:00
Marek Olšák
d17d1f53bd nir/opt_cse: update potential future plans merging copy propagation with CSE 
This matches my current understanding of nir_opt_copy_prop, including that
nir_opt_copy_prop always replaces movs with vecN.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38916>
 2025-12-13 06:41:59 +00:00