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anv: disable deferred bits on Gfx20+

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Gfx20+ doesn't do PIPELINE_SELECT, the assumption is that we can now
do any PIPE_CONTROL we want regardless of the pipeline mode.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
This commit is contained in:
Lionel Landwerlin
2024-10-21 12:08:15 +03:00
committed by Marge Bot
parent be5f5f659f
commit 23be634934
1 changed files with 2 additions and 2 deletions
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4
src/intel/vulkan/genX_cmd_buffer.c
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@@ -1714,7 +1714,7 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
if (needs_cs_stall)
bits |= ANV_PIPE_CS_STALL_BIT;
#if GFX_VER >= 12
#if GFX_VER >= 12 && GFX_VER < 20
/* From the TGL PRM, Volume 2a, "PIPE_CONTROL":
*
* "SW must follow below programming restrictions when programming
@@ -1928,7 +1928,7 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
bits &= ~ANV_PIPE_INVALIDATE_BITS;
}
#if GFX_VER >= 12
#if GFX_VER >= 12 && GFX_VER < 20
bits |= defer_bits;
#endif