Erik Faye-Lund
edca79bc41
pvr: prepare winsys files for multi-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
f473c5fa97
pvr: mark pvr_framebuffer.c as per-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
e11fac9f26
pvr: mark pvr_mrt.c as multi-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
3d84905198
pvr: mark pvr_query_compute.c as per-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Ashish Chauhan
be52ea2af7
pvr: mark pvr_queue.c as multi-arch
...
Signed-off-by: Ashish Chauhan <ashish.chauhan@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
d0d443abd7
pvr: mark pvr_sampler.c as per-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
921a04aac6
pvr: mark pvr_job_common.c as per-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
6bd378131a
pvr: mark pvr_hw_pass.c as per-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Ashish Chauhan
949e41a664
pvr: split pvr_formats.c
...
Signed-off-by: Ashish Chauhan <ashish.chauhan@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
0b97360139
pvr: split pvr_image.c
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
8c7f0ad749
pvr: mark pvr_job_context.c as per-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Ashish Chauhan
1f1a6cdadf
pvr: split pvr_spm.c
...
Signed-off-by: Ashish Chauhan <ashish.chauhan@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
8af73b5614
pvr: mark pvr_job_transfer.c as per-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
11f59c942e
pvr: mark pvr_job_render.c as per-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
d07bf4b190
pvr: mark pvr_cmd_query.c as per-arch
...
This is riddled with per-arch details; this should all be per-arch I
think.
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
bd9d87592e
pvr: mark pvr_cmd_buffer.c as per-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
6e57d71c0a
pvr: mark pvr_job_compute.c as per-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
eb56f9a200
pvr: mark pvr_tex_state.c as multi-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
6c14ff34e8
pvr: mark pvr_pass.c as multi-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:04 +01:00
Erik Faye-Lund
f789eb0d7d
pvr: mark pvr_border.c as multi-arch
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:03 +01:00
Erik Faye-Lund
120a89e2a9
pvr: split pvr_descriptor_set.c
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:03 +01:00
Erik Faye-Lund
1facaaba69
pvr: split pvr_csb.c
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:03 +01:00
Erik Faye-Lund
2c828a8825
pvr: split pvr_device.c
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:03 +01:00
Erik Faye-Lund
b5400c8ddf
pvr: factor out framebuffer-specific code
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:03 +01:00
Erik Faye-Lund
5c70230c49
pvr: factor out pvr_rt_dataset to separate module
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:03 +01:00
Erik Faye-Lund
9b3ab2c8cf
pvr: factor out cmdbuf functions from pvr_query.c
...
These functions needs to be per-arch, so let's split them out.
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:03 +01:00
Erik Faye-Lund
90f60b9b7e
pvr: limit availability of HW defs
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:03 +01:00
Erik Faye-Lund
5b3c05006d
pvr: store format-table in pvr_physical_device
...
This way we can look up in it without having to know what architecture
we're using.
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:03 +01:00
Erik Faye-Lund
49d94897af
pvr: add missing forward-decl
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:03 +01:00
Erik Faye-Lund
429e29ec42
pvr: add missing include
...
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38922 >
2025-12-19 09:52:03 +01:00
Christoph Pillmayer
cef4841d1a
pan/bi: Fix bi_find_loop_blocks for single block loops
...
Fixes: 6535a3b6eric.smith@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39018 >
2025-12-19 08:30:19 +00:00
Zan Dobersek
6bff8fd5e8
tu: use application name matching for Yooka-Laylee driconf option
...
When running Yooka-Laylee under FEX, the executable name will be the one of
the FEX binary, which the existing driconf option won't match. FEX is able
to override the executable name in newer versions, but overall it's still
more reliable to match the application name provided through Vulkan.
Fixes: 0574bfd5f4zdobersek@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39012 >
2025-12-19 07:50:40 +00:00
Ahmed Hesham
95ed8d6638
panfrost: fix get_image_width for 1D buffer images
...
Image size queries for buffer images were incorrectly using the
underlying buffer's width instead of the image view's size.
This affected `get_image_width` in OpenCL C for 1Dbuffer images, in
cases where the buffer is larger than the image to account for
padding, breaking the conformance test `test_kernel_image_methods
1Dbuffer`.
Fixes: 0efe7a6eb9ahmed.hesham@arm.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38949 >
2025-12-19 00:57:37 +00:00
Sushma Venkatesh Reddy
d9834fcaa6
compiler: Add FP8 types to GLSL type decoder
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39007 >
2025-12-19 00:09:53 +00:00
Sushma Venkatesh Reddy
d1d4e3d530
brw: Add EU assembler support for float8
...
Decode logic in Gfx12+ has become complex with the new types, so Caio
suggested that we move to the table like other gens.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39007 >
2025-12-19 00:09:53 +00:00
Jordan Justen
0088aae481
intel/brw: Add new encode/decode for use with brw_data_type_float/int
...
Rework:
* Sushma: Add BF in brw_data_type_encode, brw_data_type_decode
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39007 >
2025-12-19 00:09:53 +00:00
Jordan Justen
46e843f76e
intel/brw: Add brw_data_type_float/brw_data_type_int
...
These type encodings were first were used in dpas instructions, but
continue to be used in more places.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39007 >
2025-12-19 00:09:52 +00:00
Sushma Venkatesh Reddy
54accefed2
brw: Add BRW_TYPE_BF8 and BRW_TYPE_HF8 for float8
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39007 >
2025-12-19 00:09:52 +00:00
Mel Henning
c9ae59dec5
nvk: Set maxStorageBufferRange = maxBufferSize
...
We were previously reporting a larger maxStorageBufferRange than our
maxBufferSize, which is weird. Lower maxStorageBufferRange to match
maxBufferSize.
Fixes crucible stress.limits.buffer-update.range.storage.q0
Fixes: 65f12fde44mary@mary.zone >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39021 >
2025-12-18 23:51:50 +00:00
Ian Romanick
b967942b64
brw: Do cmod prop again after scheduling
...
After selecting the scheduling mode, do cmod prop again. It's possible
that doing cmod prop between performing a schedule and trying to
register allocate would cause a different scheduling mode to be
selected. However, this would require fully restoring the pre-schedule
set of instructions (via cloning). I have tried to implement this, and
it's harder than it looks. :(
v2: Delete unused variable `progress`. Noticed by Marge.
shader-db:
All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19967018 -> 19967006 (<.01%)
instructions in affected programs: 10652 -> 10640 (-0.11%)
helped: 4 / HURT: 0
total cycles in shared programs: 884129990 -> 884139590 (<.01%)
cycles in affected programs: 20334512 -> 20344112 (0.05%)
helped: 0 / HURT: 4
fossil-db:
Lunar Lake
Totals:
Instrs: 924967191 -> 924963460 (-0.00%); split: -0.00%, +0.00%
Cycle count: 105962414958 -> 105961925594 (-0.00%); split: -0.00%, +0.00%
Spill count: 3423582 -> 3423564 (-0.00%); split: -0.00%, +0.00%
Fill count: 4877121 -> 4876955 (-0.00%); split: -0.00%, +0.00%
Totals from 2511 (0.12% of 2018786) affected shaders:
Instrs: 12541707 -> 12537976 (-0.03%); split: -0.03%, +0.00%
Cycle count: 4816359238 -> 4815869874 (-0.01%); split: -0.01%, +0.00%
Spill count: 179536 -> 179518 (-0.01%); split: -0.03%, +0.02%
Fill count: 279407 -> 279241 (-0.06%); split: -0.07%, +0.01%
Meteor Lake, DG2, Tiger Lake, Ice Lake, and Skylake had similar results. (Meteor Lake shown)
Totals:
Instrs: 980252404 -> 980237686 (-0.00%); split: -0.00%, +0.00%
Cycle count: 91758669556 -> 91764028404 (+0.01%); split: -0.00%, +0.01%
Spill count: 3664771 -> 3664744 (-0.00%); split: -0.00%, +0.00%
Fill count: 4962078 -> 4960482 (-0.03%); split: -0.04%, +0.01%
Totals from 8472 (0.38% of 2251522) affected shaders:
Instrs: 34977623 -> 34962905 (-0.04%); split: -0.04%, +0.00%
Cycle count: 6251857553 -> 6257216401 (+0.09%); split: -0.04%, +0.13%
Spill count: 480251 -> 480224 (-0.01%); split: -0.01%, +0.00%
Fill count: 676539 -> 674943 (-0.24%); split: -0.28%, +0.05%
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38315 >
2025-12-18 15:15:20 -08:00
Ian Romanick
09450faf6a
brw: Do cmod prop again after post-RA scheduling
...
shader-db:
All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19968728 -> 19963825 (-0.02%)
instructions in affected programs: 788014 -> 783111 (-0.62%)
helped: 2503 / HURT: 0
total cycles in shared programs: 884112912 -> 884093268 (<.01%)
cycles in affected programs: 20017168 -> 19997524 (-0.10%)
helped: 1830 / HURT: 52
LOST: 0
GAINED: 6
fossil-db:
All Intel platforms had similar results. (Meteor Lake shown)
Totals:
Instrs: 980768016 -> 980172179 (-0.06%)
Cycle count: 91762351767 -> 91757280093 (-0.01%); split: -0.01%, +0.00%
Max dispatch width: 37602592 -> 37608768 (+0.02%)
Totals from 157150 (6.98% of 2251329) affected shaders:
Instrs: 107323207 -> 106727370 (-0.56%)
Cycle count: 12696754006 -> 12691682332 (-0.04%); split: -0.04%, +0.00%
Max dispatch width: 3708584 -> 3714760 (+0.17%)
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38315 >
2025-12-18 15:15:20 -08:00
Ian Romanick
08d71730ca
brw/cmod: Propagate to an instruction with same source
...
Detect cases like
mov.nz.f0.0(8) null<1>D g66<8,8,1>D
(+f0.0) sel(8) g123<1>UD g87<8,8,1>UD g84<8,8,1>UD
mov.nz.f0.0(8) null<1>D g66<8,8,1>D
(+f0.0) sel(8) g124<1>UD g88<8,8,1>UD g85<8,8,1>UD
Either MOV instruction could also be an equivalent CMP.
v2: Require no predicate, groups match, and flags written match.
v3: Add some more unit tests. Suggested by Caio.
shader-db:
All Intel platforms had similar results. (Lunar Lake shown)
total instructions in shared programs: 17203627 -> 17203590 (<.01%)
instructions in affected programs: 51432 -> 51395 (-0.07%)
helped: 37 / HURT: 0
total cycles in shared programs: 879884982 -> 879884670 (<.01%)
cycles in affected programs: 6014730 -> 6014418 (<.01%)
helped: 25 / HURT: 4
fossil-db:
Lunar Lake
Totals:
Instrs: 925092938 -> 925071952 (-0.00%); split: -0.00%, +0.00%
Cycle count: 105972157149 -> 105966120894 (-0.01%); split: -0.01%, +0.00%
Spill count: 3423592 -> 3423582 (-0.00%)
Fill count: 4876743 -> 4877121 (+0.01%); split: -0.00%, +0.01%
Max live registers: 193525293 -> 193525251 (-0.00%)
Max dispatch width: 49047056 -> 49047088 (+0.00%); split: +0.00%, -0.00%
Totals from 17714 (0.88% of 2018791) affected shaders:
Instrs: 56708169 -> 56687183 (-0.04%); split: -0.04%, +0.00%
Cycle count: 4560530879 -> 4554494624 (-0.13%); split: -0.15%, +0.01%
Spill count: 434846 -> 434836 (-0.00%)
Fill count: 807443 -> 807821 (+0.05%); split: -0.02%, +0.07%
Max live registers: 4332542 -> 4332500 (-0.00%)
Max dispatch width: 295248 -> 295280 (+0.01%); split: +0.02%, -0.01%
Meteor Lake and DG2 had similar results. (Meteor Lake shown)
Totals:
Instrs: 995075628 -> 995051291 (-0.00%); split: -0.00%, +0.00%
Cycle count: 92060967154 -> 92059311640 (-0.00%); split: -0.00%, +0.00%
Spill count: 3664664 -> 3664675 (+0.00%); split: -0.00%, +0.00%
Fill count: 4961929 -> 4961874 (-0.00%); split: -0.00%, +0.00%
Max live registers: 121480292 -> 121480184 (-0.00%)
Max dispatch width: 37947528 -> 37947496 (-0.00%)
Totals from 20569 (0.90% of 2278279) affected shaders:
Instrs: 57437989 -> 57413652 (-0.04%); split: -0.04%, +0.00%
Cycle count: 4297505238 -> 4295849724 (-0.04%); split: -0.06%, +0.03%
Spill count: 487508 -> 487519 (+0.00%); split: -0.00%, +0.00%
Fill count: 869228 -> 869173 (-0.01%); split: -0.01%, +0.00%
Max live registers: 2413028 -> 2412920 (-0.00%)
Max dispatch width: 239280 -> 239248 (-0.01%)
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
Totals:
Instrs: 1012570598 -> 1012546137 (-0.00%); split: -0.00%, +0.00%
Cycle count: 85579989052 -> 85589116671 (+0.01%); split: -0.00%, +0.01%
Spill count: 3901755 -> 3901748 (-0.00%)
Fill count: 6799383 -> 6799367 (-0.00%)
Max live registers: 122288761 -> 122288658 (-0.00%)
Totals from 20595 (0.90% of 2280449) affected shaders:
Instrs: 57764192 -> 57739731 (-0.04%); split: -0.04%, +0.00%
Cycle count: 3899898675 -> 3909026294 (+0.23%); split: -0.04%, +0.27%
Spill count: 481262 -> 481255 (-0.00%)
Fill count: 1057996 -> 1057980 (-0.00%)
Max live registers: 2412395 -> 2412292 (-0.00%)
Skylake
Totals:
Instrs: 516619178 -> 516617390 (-0.00%)
Cycle count: 57593545602 -> 57592502019 (-0.00%); split: -0.00%, +0.00%
Fill count: 860403 -> 860402 (-0.00%)
Max live registers: 87553761 -> 87553649 (-0.00%)
Totals from 1357 (0.08% of 1730068) affected shaders:
Instrs: 3575640 -> 3573852 (-0.05%)
Cycle count: 1772148559 -> 1771104976 (-0.06%); split: -0.06%, +0.00%
Fill count: 68917 -> 68916 (-0.00%)
Max live registers: 131237 -> 131125 (-0.09%)
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38315 >
2025-12-18 15:15:20 -08:00
Ian Romanick
50f2cd7366
brw/dce: Don't generate more NULL destinations after brw_lower_3src_null_dest
...
Later commits will call DCE after lowering has been performed. Creating
more things that would need lowering is problematic.
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38315 >
2025-12-18 15:15:20 -08:00
Ian Romanick
24cd8aa3b8
brw/cmod: Allow FIXED_GRF
...
Later commits will call cmod prop after register allocation. At that
time, there is only FIXED_GRF.
No shader-db or fossil-db changes on any Intel platform.
v2: FIXED_GRF uses subnr instead of offset. Add a unit test to
demonstrate the issue.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com > [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38315 >
2025-12-18 15:15:20 -08:00
Ian Romanick
d7227b11a1
brw: elk: Disable can_do_cmod for MACH
...
PRMs for G35 (Gfx4) through Ivy Bridge (Gfx7) all say that conditional
modifiers are allowed for MACH. Starting with Haswell (Gfx7.5), this
seems to be removed. This function doesn't have any way to know the
platform, so false is returned for all platforms.
No shader-db or fossil-db changes on any Intel platform.
Prevents a failure in "brw: Do cmod prop again after post-RA scheduling"
in piglit's builtin-uint-mad_sat-1.0.generated.cl.
Cc: stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38315 >
2025-12-18 15:15:20 -08:00
Ian Romanick
ba30794847
brw/cmod: Don't propagate between instructions in different groups
...
The group implicity selects which flags the instruction can write. This
was discovered while working on another set of changes that could change
some logical operations into predicated MOV instructions.
Prevents regressions later in the series in
dEQP-VK.graphicsfuzz.cov-loop-fragcoord-identical-condition.
No shader-db or fossil-db changes on any Intel platform.
v2: Update the comment in the test case. Suggested by Caio.
Fixes: 95ac3b1daecaio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38315 >
2025-12-18 15:15:20 -08:00
Ian Romanick
c0fb93506b
brw: Add brw_reg::is_grf
...
v2: Add a function comment. Suggested by Caio.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38315 >
2025-12-18 15:15:20 -08:00
Benjamin Cheng
fa8b0b6bbb
radv/video: Enable write combine for decode
...
Reviewed-by: David Rosca <david.rosca@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39025 >
2025-12-18 15:25:57 -05:00
Dmitry Baryshkov
4315c28739
gfxstream: don't dump genvk.py args to generated files
...
Full command lines include full path to the output file, which triggers
reproducibility warnings (e.g. in Yocto builds). Drop the args and print
only a basename of the script used to generate the file.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38875 >
2025-12-18 18:52:19 +00:00
hwandy
ffbe6470a2
anv: fix a memory leak in slab allocator.
...
An example when the memory leak happens: requested_size = 4 and alignment = 65536 in anv_slab_bo_alloc:
The alloc_size = 65536 and requested = 4 in this case.
The group to allocate the entry is the group of size 65536 based on the entry size,
while the group to reclaim the entry is the group of size 4 due to the bo->size is
registered as the requested_size=4 and used in anv_slab_bo_free.
That means, the entry is allocated in group[order of size 65535]->free,
moved from group[order of size 65535]->free to the user, and then moved
to group[order of size 4]->reclaim, so the entries is accumulated in
group[order of size 4]->reclaim and group[order of size 65535] keeps
allocating new entries and leading to OOM.
The solution is to use `bo->actual_size` to get the group in pb_slab_bo_free using the allocation size.
Fixes: dabb012423https://gitlab.freedesktop.org/mesa/mesa/-/issues/14396
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Signed-off-by: hwandy <hwandy@google.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38989 >
2025-12-18 18:25:54 +00:00
