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anv: introduce an new virtual pipecontrol flag for BTI change

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
This commit is contained in:
Lionel Landwerlin
2025-11-27 12:01:18 +00:00
committed by Marge Bot
parent 682f907228
commit e5fc567f49
5 changed files with 27 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/intel/vulkan/anv_private.h
View File

@@ -4026,6 +4026,19 @@ enum anv_pipe_bits {
* L3.
*/
ANV_PIPE_END_OF_PIPE_SYNC_FORCE_FLUSH_L3_BIT = (1 << 25),
/* This bit does not exist directly in PIPE_CONTROL. It helps to track post
* fast clear flushes. BSpec 57340 says in relation to fast clear flushes
* that "RESOURCE_BARRIER allows hardware to opportunistically combine this
* operation with previous RESOURCE_BARRIER commands potentially reducing
* overall synchronization cost", that appears to be untrue as experienced
* with
* dEQP-VK.synchronization.op.single_queue.barrier.write_clear_color_image_read_copy_image_to_buffer.image_128x128_r8_unorm
*
* If a PIPE_CONTROL is emitted this should be converted to
* ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT.
*/
ANV_PIPE_RT_BTI_CHANGE = (1 << 26),
};
/* These bits track the state of buffer writes for queries. They get cleared

2
src/intel/vulkan/anv_util.c
View File

@@ -147,6 +147,8 @@ anv_dump_pipe_bits(enum anv_pipe_bits bits, struct log_stream *stream)
mesa_log_stream_printf(stream, "+utdp_flush ");
if (bits & ANV_PIPE_CCS_CACHE_FLUSH_BIT)
mesa_log_stream_printf(stream, "+ccs_flush ");
if (bits & ANV_PIPE_RT_BTI_CHANGE)
mesa_log_stream_printf(stream, "+rt-bti-change ");
}
const char *

4
src/intel/vulkan/genX_blorp_exec.c
View File

@@ -315,7 +315,7 @@ blorp_exec_on_render(struct blorp_batch *batch,
anv_add_pending_pipe_bits(cmd_buffer,
VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT,
VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT,
ANV_PIPE_RT_BTI_CHANGE,
"before blorp BTI change");
}
#endif
@@ -383,7 +383,7 @@ blorp_exec_on_render(struct blorp_batch *batch,
anv_add_pending_pipe_bits(cmd_buffer,
VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT,
VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT,
ANV_PIPE_RT_BTI_CHANGE,
"after blorp BTI change");
}
#endif

14
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -1721,6 +1721,12 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
if (needs_cs_stall)
bits |= ANV_PIPE_CS_STALL_BIT;
if (bits & ANV_PIPE_RT_BTI_CHANGE) {
bits &= ~ANV_PIPE_RT_BTI_CHANGE;
bits |= ANV_PIPE_STALL_AT_SCOREBOARD_BIT |
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
}
#if GFX_VER >= 12 && GFX_VER < 20
/* From the TGL PRM, Volume 2a, "PIPE_CONTROL":
*
@@ -3074,8 +3080,7 @@ genX(cmd_buffer_update_color_aux_op)(struct anv_cmd_buffer *cmd_buffer,
* clear pass, to ensure correct ordering between pixels.
*/
add_pending_pipe_bits_for_color_aux_op(
cmd_buffer, next_aux_op,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT);
cmd_buffer, next_aux_op, ANV_PIPE_RT_BTI_CHANGE);
#elif GFX_VERx10 == 125
/* From the ACM Bspec 47704 (r52663), "Render Target Fast Clear":
@@ -3166,8 +3171,7 @@ genX(cmd_buffer_update_color_aux_op)(struct anv_cmd_buffer *cmd_buffer,
* RT flush = 1
*/
add_pending_pipe_bits_for_color_aux_op(
cmd_buffer, next_aux_op,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT);
cmd_buffer, next_aux_op, ANV_PIPE_RT_BTI_CHANGE);
#elif GFX_VERx10 == 120
/* From the TGL PRM Vol. 9, "Color Fast Clear Synchronization":
@@ -6038,7 +6042,7 @@ void genX(CmdBeginRendering)(
anv_add_pending_pipe_bits(cmd_buffer,
VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT,
VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT,
ANV_PIPE_RT_BTI_CHANGE,
"change RT");
}
#endif

2
src/intel/vulkan/genX_cmd_draw.c
View File

@@ -714,7 +714,7 @@ cmd_buffer_maybe_flush_rt_writes(struct anv_cmd_buffer *cmd_buffer,
anv_add_pending_pipe_bits(cmd_buffer,
VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT,
VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT,
ANV_PIPE_RT_BTI_CHANGE,
"change RT due to shader outputs");
#endif
}