a2ab143b75
cleanups, comments
2007-11-29 08:13:16 -07:00
a7e1b4456a
Move _mesa_load_tracked_matrices() from TNL module to prog_statevars.c
2007-11-29 08:13:16 -07:00
dc88a96631
r200: Fix texture format regression on big endian systems.
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See https://bugs.freedesktop.org/show_bug.cgi?id=13324 .
Also use tx_table_be for VALID_FORMAT, in case r200SetTexImages ever gets
called for MESA_FORMAT_RGB888.
2007-11-28 10:20:04 +01:00
d8fcb504a4
i965: update RefCount when using Vertex/Fragment program.
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It makes quake4-demo works well on 965.
2007-11-28 09:46:43 +08:00
16099c15f5
remove drawable from hash table when window is deleted (see bug 13091)
2007-11-27 18:22:42 -07:00
5c64e6885d
use DEFAULT_SOFTWARE_DEPTH_BITS
2007-11-27 18:18:25 -07:00
27028fcf74
minor additions to avoid FAQs
2007-11-27 10:31:55 -07:00
5ef3a2c06d
document GLSL float f/F suffix bug
2007-11-27 10:31:55 -07:00
4fe3bf2d77
set fp->UsesKill when emitting OPCODE_KIL
2007-11-27 10:31:55 -07:00
92e4090b4c
add a few more logicop modes, simplify code
2007-11-27 10:31:55 -07:00
74cd0b459f
improve 24-bit Z to 32-bit Z conversion
2007-11-27 10:31:55 -07:00
46e03d584a
i965: The jump instruction count is added
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to IP pre-increment, and should point to
the first instruction after the do instruction
of the do-while block of code
2007-11-27 09:45:32 +08:00
a8fee3a498
i915: Catch cases where not all state is emitted for a new batchbuffer.
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This could lead to incorrect rendering or even lockups.
2007-11-26 17:49:29 +01:00
63e6bfe8db
i915: Some additional blit fixes and assertions.
2007-11-26 17:35:35 +01:00
42108629e8
libGL: Make sure a valid value is returned for GLX_BIND_TO_MIPMAP_TEXTURE_EXT.
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If the server didn't send a value, assume it's not supported.
A more generic solution might be better for this kind of problem, but an
attempt for this failed (see https://bugs.freedesktop.org/show_bug.cgi?id=9264 )
and this allows compiz to work with drivers that support
GL_EXT_framebuffer_object.
2007-11-25 14:20:36 +01:00
7dd5ced962
intel: Fix relative symlinks.
2007-11-25 14:17:02 +01:00
be1fa5b3d7
better test of point attenuation
2007-11-23 16:19:25 -07:00
88b067cb04
#define GL_GLEXT_PROTOTYPES to silence warning
2007-11-23 14:35:46 -07:00
999b55663a
Consolidate texture fetch code and use partial derivatives when possible.
2007-11-23 12:01:57 -07:00
ba16243884
Fix parsing of gl_FrontLightModelProduct.sceneColor, don't segfault on variable array indexes.
2007-11-23 10:25:48 -07:00
c14d969a69
need to check border width in sample_linear_2d() - fixes failed assertion in texwrap.c test
2007-11-23 09:14:39 -07:00
0fd679a190
Consolidate point size computation, clamping in get_size().
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Also, apply user-defined clamp limits to point size even when not using
attentuation or program-computed size.
2007-11-22 09:34:38 -07:00
ccb1c9df00
Print point/line size range limits
2007-11-22 09:34:38 -07:00
3d51c79001
fix z buffer read/write issue with rv100-like chips and old ddx
2007-11-22 02:49:15 +01:00
93c98a4669
[965] Replace 965 texture format code with common code.
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The only functional difference should be that 965 now gets the optimization
where textures default to 16bpp when the screen is 16bpp.
2007-11-20 11:30:12 -08:00
e962997429
[965] Remove dead exec vfmt code which was replaced by generic vbo code.
2007-11-20 11:30:10 -08:00
827e72de75
clamp lambda to Min/MaxLod
2007-11-20 08:24:46 -07:00
3821d15e06
[965] Add INTEL_DEBUG=fall debugging output.
2007-11-19 15:29:31 -08:00
27674c4135
[965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.
2007-11-19 15:28:26 -08:00
87373e3072
fix some texture format assertions, etc
2007-11-19 10:37:54 -07:00
22a374fc3f
fix out-of-bounds array index (ix=-1)
2007-11-19 09:55:47 -07:00
f00a64999c
[intel] Add 965 support to shared intel_blit.c
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This requires that regions grow a marker of whether they are tiled or not,
because fence (surface) registers are ignored by the 965 2D engine.
2007-11-16 17:29:30 -08:00
9b461d4d02
[i915] Pass static region names in so debugging says more than "static region".
2007-11-16 16:18:30 -08:00
5ef6803b7a
[intel] Move additional code to be shared from intel_context.h to intel/.
2007-11-16 16:05:11 -08:00
5cdf3972de
[intel] Move intel_tex.h into place, forgotten in the previous commit.
2007-11-16 15:51:34 -08:00
8775bf475b
[965] Add batchbuffer decode for several more packets.
2007-11-16 15:44:11 -08:00
a66413874d
[intel] Fix typos in intel_chipset.h macros.
2007-11-16 15:36:18 -08:00
3bd07ba0d4
[i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them.
2007-11-16 15:36:18 -08:00
f7e0513d70
[i915] Reenable batchbuffer debug under INTEL_DEBUG=bat.
2007-11-16 15:36:18 -08:00
152aa6350d
[intel] Add some doxygen notes on what the bufmgr_fake block members mean.
2007-11-16 15:36:18 -08:00
c29e9e534e
[intel] Add a simple relocation cache to the fake buffer manager.
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This is required for 965 performance, as it avoids a lot of repeated data
uploads of the state caches due to surface offsets in them.
2007-11-16 15:36:18 -08:00
4bc625e378
[intel] Assert against 0-sized buffers in dri_bufmgr_fake.c.
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They shouldn't be created, and this often helps catch stupid issues.
2007-11-16 15:36:18 -08:00
00eb5635c6
[intel] Add support for multiple levels of relocation in bufmgr_fake.
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This is required for 965 support, which has relocations in other places than
just the batchbuffer.
2007-11-16 15:36:18 -08:00
df3c530bed
[i915] Push locking in intelClearWithTris down inside meta_draw_poly.
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The lock coverage and checks for cliprects were unneeded since the batchbuffer
will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from
intelClearWithBlit.
This makes the locking requirements of i915 meta_draw_quad match i965
meta_draw_quad.
2007-11-16 15:36:18 -08:00
8211b20026
added z/s keys to reset/step rotation
2007-11-16 15:19:05 -07:00
fb69fe58a0
Only emit texcoords for enabled units. Enable/disable units with 0..7 keys.
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Also, asst. clean-ups.
2007-11-16 15:19:05 -07:00
96ba38a450
fix bogus assumption if ddx has set up surface reg for z buffer
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this is wrong since even if ddx has not set up a surface reg to cover the z
buffer we should pretend it has on those rv100 chips since they presumably do
not do z buffer tiling if not using hyperz, so we can use linear addressing
just the same. Doesn't seem to fix #13080 , but it's wrong anyway and the bug
almost certainly broke newer non-tcl chips.
2007-11-15 01:13:16 +01:00
dab7c810e9
fix position invariant vertex programs for sw-tnl
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do the same math as for fixed function pipe, including
user clip planes.
(mostly resurrected from the dead t_vb_arbprogram.c code)
2007-11-15 00:52:38 +01:00
f6ab1347d6
remove dependency on libGLU
2007-11-12 08:02:09 -07:00
b87ce5be82
add glw.pc.in to tarball list, remove from DEPEND_FILES
2007-11-12 07:51:55 -07:00
Brian