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Author SHA1 Message Date
Samuel Pitoiset 8ea46b14fa ci: update VKCTS main to 76c1572eaba42d7ddd9bb8eb5788e52dd932068e 
RADV is the only driver using VKCTS main.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34299>
 2025-04-14 08:24:14 +00:00
Samuel Pitoiset 410f7f9f6e radv: only enable DCC for invisible VRAM on GFX12 
DCC should only be allowed on invisible VRAM, otherwise the CPU could
read the data and it will read garbage if it's compressed.

This also caused GPU hangs after suspend/resume probably because
some buffers were compressed when moved back from GTT to VRAM.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12962
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12922
Fixes: 9af11bf306 ("radv: add initial DCC support on GFX12")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34347>
 2025-04-14 07:39:33 +00:00
Samuel Pitoiset 75be860eec radv: use paired context regs when optimal on GFX12 
CP is very slow on GFX12 and parsing the packet header is the main
bottleneck. Using paired context regs reduce the number of packet
headers and it should be more optimal.

It doesn't seem worth when only one context reg is emitted (one packet
header and same number of DWORDS) or when consecutive context regs are
emitted (would increase the number of DWORDS).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34421>
 2025-04-14 06:18:13 +00:00
Samuel Pitoiset f92f50c58a radv: add macros for paired context registers on GFX12 
Imported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34421>
 2025-04-14 06:18:13 +00:00
Job Noorman 35ec960f6f ir3: run cp after ir3_imm_const_to_preamble 
Now that ir3_cp has an option to not lower immediates to const
registers, we can use it after ir3_imm_const_to_preamble instead of
manually propagating immediates.

This fixes a lot of missed opportunities for early-preamble as we didn't
propagate the mova1 immediate which a caused a GPR to be used in many
preambles.

Totals:
Instrs: 49704517 -> 49703700 (-0.00%); split: -0.16%, +0.16%
CodeSize: 103917968 -> 103187072 (-0.70%); split: -0.82%, +0.11%
NOPs: 8516944 -> 8511764 (-0.06%); split: -0.78%, +0.72%
MOVs: 1534023 -> 1536385 (+0.15%); split: -1.12%, +1.27%
Full: 1816517 -> 1816548 (+0.00%); split: -0.05%, +0.06%
(ss): 1162108 -> 1161490 (-0.05%); split: -1.03%, +0.98%
(sy): 611398 -> 610311 (-0.18%); split: -0.80%, +0.62%
(ss)-stall: 4384529 -> 4388096 (+0.08%); split: -1.22%, +1.30%
(sy)-stall: 17858701 -> 17837101 (-0.12%); split: -0.87%, +0.74%
STPs: 25096 -> 25491 (+1.57%); split: -0.05%, +1.63%
LDPs: 37635 -> 38030 (+1.05%); split: -0.03%, +1.08%
Preamble Instrs: 12589113 -> 11391946 (-9.51%); split: -9.75%, +0.24%
Early Preamble: 115946 -> 122893 (+5.99%); split: +6.05%, -0.06%
Cat0: 9374513 -> 9370393 (-0.04%); split: -0.71%, +0.67%
Cat1: 2443348 -> 2446546 (+0.13%); split: -0.82%, +0.95%
Cat2: 18731502 -> 18731478 (-0.00%); split: -0.00%, +0.00%
Cat7: 1410092 -> 1410221 (+0.01%); split: -0.61%, +0.62%

Totals from 39189 (23.81% of 164575) affected shaders:
Instrs: 30656115 -> 30655298 (-0.00%); split: -0.26%, +0.26%
CodeSize: 61714230 -> 60983334 (-1.18%); split: -1.37%, +0.19%
NOPs: 6074700 -> 6069520 (-0.09%); split: -1.10%, +1.01%
MOVs: 1010392 -> 1012754 (+0.23%); split: -1.70%, +1.93%
Full: 617108 -> 617139 (+0.01%); split: -0.16%, +0.16%
(ss): 778842 -> 778224 (-0.08%); split: -1.54%, +1.46%
(sy): 362803 -> 361716 (-0.30%); split: -1.35%, +1.05%
(ss)-stall: 3203827 -> 3207394 (+0.11%); split: -1.67%, +1.78%
(sy)-stall: 9507680 -> 9486080 (-0.23%); split: -1.63%, +1.40%
STPs: 23004 -> 23399 (+1.72%); split: -0.06%, +1.77%
LDPs: 33942 -> 34337 (+1.16%); split: -0.04%, +1.20%
Preamble Instrs: 8090918 -> 6893751 (-14.80%); split: -15.18%, +0.38%
Early Preamble: 12246 -> 19193 (+56.73%); split: +57.25%, -0.52%
Cat0: 6656706 -> 6652586 (-0.06%); split: -1.00%, +0.94%
Cat1: 1546399 -> 1549597 (+0.21%); split: -1.30%, +1.50%
Cat2: 11642214 -> 11642190 (-0.00%); split: -0.00%, +0.00%
Cat7: 943911 -> 944040 (+0.01%); split: -0.91%, +0.92%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34397>
 2025-04-14 04:37:28 +00:00
Job Noorman 226ec669d8 ir3/cp: ignore alias sources for sam.s2en 
ir3_cp asserts that the first source of a sam.s2en is a collect which
isn't necessarily true after creating alias registers.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34397>
 2025-04-14 04:37:28 +00:00
Job Noorman 1618c2495b ir3/cp: add option to disable immediate to const lowering 
This will allow it to be used after ir3_imm_const_to_preamble so that we
don't have to do the propagation of immediates manually there.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34397>
 2025-04-14 04:37:27 +00:00
Job Noorman 6546a40225 ir3: remove spaces in shader stats 
The shaderdb scripts don't like them.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34397>
 2025-04-14 04:37:27 +00:00
Trigger Huang 1e709dbea3 radeonsi: Change program seqnece for perf counters 
Based on the sample usage described in
https://registry.khronos.org/OpenGL/extensions/AMD/AMD_performance_monitor.txt
, the value read from SQ_0004 is always 0, while other counters can be read
successfully.

This patch will sync the program sequence with the following link
https://github.com/GPUOpen-Drivers/AMDVLK/releases/tag/v-2023.Q3.3
With it, SQ_0004 and also other counters can be raed successfully

Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34360>
 2025-04-14 10:23:46 +08:00
Karol Herbst fc7badeac0 zink: don't apply the map_offset when mapping a staging resource in zink_buffer_map 
Fixes regressions in the OpenCL CTS allocation tests.

Fixes: 5d46e2bf3c ("zink: implement unsynchronized staging uploads for buffers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34494>
 2025-04-12 17:42:53 +00:00
Faith Ekstrand fadac25b0c nil: Multiply by array_stride_B instead of adding 
Fixes: 5577128c83 ("nil: Rewrite the TIC code in Rust")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34495>
 2025-04-12 17:04:40 +00:00
Faith Ekstrand 5c81b3546f nvk/nvkmd: Check the correct flag for the Kepler GART workaround 
Fixes: 1db57bb414 ("nvk/nvkmd: Rework memory placement flags")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34495>
 2025-04-12 17:04:40 +00:00
Konstantin Seurer 985f5e0875 lavapipe: Do not emit aabb handling if no isec shader is used 
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34003>
 2025-04-12 17:22:50 +02:00
Konstantin Seurer 7113620625 lavapipe: pre-load tmax 
tmax is lowered to scratch with ray tracing pipelines.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34003>
 2025-04-12 17:22:44 +02:00
Konstantin Seurer c1a620ae19 lavapipe: Run nir optimizations on ray tracing pipelines 
Improves performance by 10%.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34003>
 2025-04-12 17:22:37 +02:00
Konstantin Seurer cdb2e3d2b5 lavapipe: Prefetch 56 bytes of node data during ray traversal 
Almost all node types need around 56 bytes of data. This patch fetches
this data in a less divergent block.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34003>
 2025-04-12 17:22:27 +02:00
Konstantin Seurer 676e26aed5 radv: Fix rayTracingPositionFetch with multiple geometies 
The fix adds more indirections to avoid increasing register pressure by
tracking the primitive address.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34460>
 2025-04-11 22:26:08 +00:00
Aleksi Sapon 77eb58baad draw: fix gl_PrimitiveID in tessellation 
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33415>
 2025-04-11 22:01:05 +00:00
Konstantin Seurer cb31b5a958 clc,libcl: Clean up CL includes 
This patch does a couple of things to make CL integration with drivers
as seamless as possible:
- We pull in opencl-c.h and opencl-c-base.h to stop relying on system
  headers.
- Parts of libcl.h are moved to new headers that are incomplete CL-safe
  variants of libc headers.
- A couple of util headers are changed to remove now unnecessary
  __OPENCL_VERSION__ guards and make more headers CL safe.
- Drivers now include src/compiler/libcl and use headers like
  macros.h,u_math.h instead of libcl.h.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33576>
 2025-04-11 21:27:37 +00:00
Konstantin Seurer a80fab3e87 clc: Allow bitfields 
bitfields are not officially supported by Open CL but there is a clang
extension that adds support.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33576>
 2025-04-11 21:27:37 +00:00
Konstantin Seurer ed07aab147 clc: Print errors when initializing clang fails 
It's nice to know what actually went wrong.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33576>
 2025-04-11 21:27:37 +00:00
Dmitry Baryshkov b9c6afd3a7 meson: disable SIMD blake optimisations on x32 host 
On X.org startup libgallium crashes on x32 hosts inside
blake3_hash_many_sse41(), most likely because of the different pointer
size. Disable SIMD blake implementation if x32 is detected.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34453>
 2025-04-11 20:57:38 +00:00
Kenneth Graunke eb1ec9cf8e brw: Don't assert about MAX_VGRF_SIZE in brw_opt_split_virtual_grfs() 
This allows us to create temporary VGRFs that are larger than
MAX_VGRF_SIZE(devinfo), which will be split eventually.  They may not
be split on the initial pass, because we may need LOAD_PAYLOAD lowering,
copy propagation, and so on to occur first.  So we allow registers to
exceed that size initially.

The "Register allocation relies on split_virtual_grfs()" assertion in
brw_reg_allocate.cpp still asserts that all VGRFs which reach the
register allocator have been properly split.

One case where this is useful is for vectorizing convergent block loads.
We create temporaries to splat the SIMD1 values out to SIMD(N), which
can lead to some very large temporaries.  However, copy propagation and
so on ultimately eliminate these and they'll get split down to proper
sizes or elided entirely in the end.

(Note: both this and the prior commits from this merge request are
 needed to close the linked issue.)

Cc: mesa-stable
Reviewed-by: Matt Turner <mattst88@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12324
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34461>
 2025-04-11 20:34:51 +00:00
Kenneth Graunke a45583f078 brw: Use live->max_vgrf_size in pre-RA scheduling 
Post-RA scheduling doesn't use liveness analysis, so we continue using
MAX_VGRF_SIZE(devinfo).  But for pre-RA scheduling, we now use
live->max_vgrf_size.

This helps get us to a place where we can emit arbitrarily large VGRFs
early on in compilation, but which will be split and cleaned up prior to
register allocation.  It may also allocate smaller arrays in practice
since MAX_VGRF_SIZE(devinfo) assumes the worst case scenario for things
we actually could need to allocate.

Cc: mesa-stable
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34461>
 2025-04-11 20:34:51 +00:00
Kenneth Graunke 4b27b5895c brw: Use live->max_vgrf_size in register coalescing 
We already require liveness, so just use the actual maximum size we saw
instead of a hardcoded pessimal size.

Cc: mesa-stable
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34461>
 2025-04-11 20:34:51 +00:00
Kenneth Graunke ea468412f6 brw: Track the largest VGRF size in liveness analysis 
We're already looking at this data to calculate the per-component
vars_from_vgrf[] and vgrf_from_vars[] mappings, so just record the
largest VGRF size while we're here.  This will allow passes to size
arrays based on the actual size needed, rather than hardcoding some
fixed size.  In many cases, MAX_VGRF_SIZE(devinfo) is larger than
necessary, because e.g. vec5 sparse sampling results aren't used.
Not hardcoding this means we can also temporarily handle very large
VGRFs which we know will be split eventually, without having to
increase the maximum which is ultimately used for RA classes.

Cc: mesa-stable
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34461>
 2025-04-11 20:34:51 +00:00
Alyssa Rosenzweig 4a299bea27 hk: drop soft fault assumption in hk_buffer_addr_range 
fixes test_index_buffer_edge_case_stream_output without soft fault.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34486>
 2025-04-11 20:16:01 +00:00
Alyssa Rosenzweig 0f9b396588 hk: advertise sparseResidencyBuffer 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34486>
 2025-04-11 20:16:01 +00:00
Alyssa Rosenzweig 4b119b36c8 hk: use ro maps 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34486>
 2025-04-11 20:16:01 +00:00
Alyssa Rosenzweig f3272ebab8 hk: bind for sparse emulation 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34486>
 2025-04-11 20:16:01 +00:00
Alyssa Rosenzweig fb71b8a4ee asahi: fix zero bo leak 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34486>
 2025-04-11 20:16:01 +00:00
Alyssa Rosenzweig 546bc893f1 asahi: add sparse emu helpers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34486>
 2025-04-11 20:16:01 +00:00
Alyssa Rosenzweig c2d00c94b1 asahi: shrink VA space for sparse emulation 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34486>
 2025-04-11 20:16:01 +00:00
Eric Engestrom 1f718c5b0f zink+anv/ci: document a bunch of flaky glx tests that have been preventing merges all day 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34484>
 2025-04-11 19:51:10 +00:00
Caio Oliveira 2ed79f80ba nir/load_store_vectorize: Skip new bit-sizes that are unaligned with high_offset 
Otherwise this would require combining two values to produce a single
(new bit-size) channel, which vectorize_stores() don't handle.  The pass
can still keep trying smaller bit-sizes.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12946
Fixes: ce9205c03b ("nir: add a load/store vectorization pass")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34414>
 2025-04-11 19:17:17 +00:00
Caio Oliveira eaf9371fd5 broadcom/ci: Skip test due to timeout 
A later change will cause this test to take more than the
timeout limit, so skip it per maintainers request.
Suggested by Iago.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34414>
 2025-04-11 19:17:17 +00:00
José Roberto de Souza 20bf10ba17 drm-uapi: Sync xe_drm.h 
Sync with:
commit cf05922d63e2ae6a9b1b52ff5236a44c3b29f78c
Merge: a82866fbecca6 bfef148f3680e
Author: Dave Airlie <airlied@redhat.com>

    Merge tag 'drm-intel-gt-next-2025-03-12' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34457>
 2025-04-11 18:35:49 +00:00
José Roberto de Souza 68a617076d intel/perf: Update intel_perf to match xe_drm.h 
There was a mismatch between drm-next version of xe_drm.h and the one
in https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30142.
So this does the necessary changes to build with current and new
xe_drm.h

Fixes: 2a828c35a1 ("intel/perf: add eu stall sampling support")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34457>
 2025-04-11 18:35:49 +00:00
Timur Kristóf 371b1bf789 radv: Don't call nir_opt_varyings a second time when unnecessary. 
When nir_opt_varyings doesn't make progress the first time,
it should not be necessary to call it a second time.

No Fossil DB changes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33880>
 2025-04-11 18:01:47 +00:00
Timur Kristóf 403b3958c1 radv: Move preparation and fixup to separate loops in varying optimization. 
This is to stop calling nir_shader_gather_info repeatedly for
some stages, and also as a pre-requisite to the work in the next commits.

No Fossil DB changes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33880>
 2025-04-11 18:01:47 +00:00
Timur Kristóf a98186bbf6 radv: Refactor loops in radv_graphics_shaders_link_varyings. 
No functional changes, just improved code readability.

No Fossil DB changes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33880>
 2025-04-11 18:01:47 +00:00
Timur Kristóf 1942227e73 radv: Inline radv_graphics_shaders_link_varyings_{first/second}. 
The first step of reorganizing this code.

No Fossil DB changes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33880>
 2025-04-11 18:01:47 +00:00
Timur Kristóf 412af41258 radv: Add radv_foreach_stage to ForEachMacros again. 
This was lost when .clang-format was removed
from the amd folder.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33880>
 2025-04-11 18:01:47 +00:00
Erico Nunes 23c0d64e24 panvk: disable VK_EXT_image_drm_format_modifier for arch < 10 
VK_KHR_sampler_ycbcr_conversion is a dependency from the
VK_EXT_image_drm_format_modifier spec. panvk arch < 10 still
doesn't support it, so VK_EXT_image_drm_format_modifier should
not be exposed.
Otherwise, a Vulkan validation error is triggered for users of
VK_EXT_image_drm_format_modifier and it may cause applications
to fail to create a device.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34458>
 2025-04-11 16:36:52 +00:00
Lionel Landwerlin 243c01c703 anv/iris: implement Wa_18040903259 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34433>
 2025-04-11 13:54:35 +00:00
Lionel Landwerlin d123aedfc7 anv: remove ALWAYS_INLINE from globally visible functions 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34433>
 2025-04-11 13:54:35 +00:00
Lionel Landwerlin bcaf08b47c intel/dev: remove ADLN references 
Not used anymore, just use the existing ADL definitions.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34433>
 2025-04-11 13:54:35 +00:00
Lionel Landwerlin 938f79ed82 anv: update Wa_1607156449 to use WA infrastructure 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34433>
 2025-04-11 13:54:35 +00:00
Lionel Landwerlin 77a3572ae0 iris: update Wa_1607156449 to use WA infrastructure 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34433>
 2025-04-11 13:54:35 +00:00
Georg Lehmann d046ecf95a nir/opt_algebraic: optimize open coded ffract 
Foz-DB Navi21:
Totals from 274 (0.34% of 79789) affected shaders:
Instrs: 522630 -> 522181 (-0.09%); split: -0.09%, +0.01%
CodeSize: 2880668 -> 2878940 (-0.06%); split: -0.07%, +0.01%
VGPRs: 14488 -> 14464 (-0.17%)
Latency: 4092358 -> 4091243 (-0.03%); split: -0.04%, +0.01%
InvThroughput: 1014148 -> 1013471 (-0.07%); split: -0.07%, +0.00%
VClause: 11646 -> 11639 (-0.06%)
SClause: 18614 -> 18611 (-0.02%)
Copies: 56248 -> 56309 (+0.11%); split: -0.05%, +0.16%
PreVGPRs: 13649 -> 13647 (-0.01%)
VALU: 359733 -> 359285 (-0.12%); split: -0.13%, +0.01%
SALU: 59719 -> 59720 (+0.00%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33369>
 2025-04-11 12:36:02 +00:00