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Author SHA1 Message Date
Eric Engestrom
47f6e24ad5 meson: move tsan-blacklist.txt to build-support with the other build support files 
Fixes: 0d46e0e88b ("meson: Add blacklist when compiling with tsan")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28996>
 2024-05-01 07:05:12 +00:00
Kenneth Graunke
84139470a5 intel/brw: Use VEC for emit_unzip() 
Helps make SIMD-split code more SSA-friendly.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:54 -07:00
Kenneth Graunke
1b54b4fad5 intel/brw: Use VEC for NIR vec*() sources 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:50 -07:00
Kenneth Graunke
d4563747d9 intel/brw: Use VEC for output stores 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:49 -07:00
Kenneth Graunke
f0c29c9b71 intel/brw: Use VEC for FS outputs 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:49 -07:00
Kenneth Graunke
cbe7a13f2b intel/brw: Use VEC for TCS/TES/GS input/output loads 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:48 -07:00
Kenneth Graunke
a94e1bd0ac intel/brw: Use VEC for gl_FragCoord 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:47 -07:00
Kenneth Graunke
d0a24496fd intel/brw: Use VEC for load_const 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:45 -07:00
Kenneth Graunke
3c867bf2c7 intel/brw: Add a new VEC() helper. 
This gathers a number of sources into a contiguous vector register.
Eventually, the plan is that it will use a MOV for a single source,
or LOAD_PAYLOAD for multiple sources.  For now, it emits a series of
MOVs to allow us to rewrite a bunch of existing code to use the new
helper, then change them all over at once later.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:42 -07:00
Kenneth Graunke
c194df565a intel/brw: Don't include unnecessary undefined values in texture results 
When emitting a sampler message, we allocate a temporary destination
large enough to hold 4 values (or 5 for sparse).  This is the maximum
size needed to hold any result.  However, we shrink the size written by
the sampler message to skip writing any trailing components that NIR
tells us are never read.  So we may not write the entire temporary.

The NIR texture instruction has a destination VGRF which is sized
assuming that all components are present.  We issue a LOAD_PAYLOAD
instruction to copy our sampler result temporary to the NIR destination.
When we reduce the response length of the sampler messages, then some of
these temporary components have undefined values.  The correct way to
indicate that is by using a BAD_FILE source.  Unfortunately, we were
naively reading offsets of the temporary that were never written, but
are still part of a larger VGRF.  This complicates things.

For example, sampling and only using RGB (not RGBA) was producing this:

   txl_logical(8) (written: 3) vgrf3+0.0:F, ...
   undef(8) (written: 4) vgrf4:UD
   load_payload(8) (written: 4) vgrf4:F, vgrf3+0.0:F, vgrf3+1.0:F, vgrf3+2.0:F, vgrf3+3.0:F

The last source, vgrf3+3.0:F, is undefined, and should be BAD_FILE.
Doing so allows VGRF splitting and other optimizations to work better.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:41 -07:00
Kenneth Graunke
e42914529a intel/brw: Support CSE on more ops 
This has no changes in shader-db or fossil-db, surprisingly, but at
least CSEL will be useful shortly.  Presumably the others may matter
somewhere.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:40 -07:00
Kenneth Graunke
ed3e4c16dc intel/brw: Do not create empty basic blocks when removing instructions 
If there's only a single instruction in a basic block, then removing it
would create an empty block.  We seem to have trouble representing those
as there are no instructions with an IP inside the block; several places
mess up connections.  While most blocks end in control flow instructions
(which are rarely eliminated), ones preceding a DO instruction may end
in an ordinary instruction.  This makes such blocks tricky to merge with
adjacent blocks - they may be between loops.  Any optimization pass may
may find such an instruction and want to eliminate it, and most of them
are unprepared to perform such CFG link surgery.  Nor do we want to make
every pass aware of this issue.

To work around this, we simply replace an instruction with a NOP when
removing it from a block containing only that instruction, leaving the
block in place.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:39 -07:00
Kenneth Graunke
391da3610c intel/brw: Print W/UW immediates correctly 
We were printing 24w as 0x180018d which not only scarily shows the
wrong type, but also the replicated format of the word.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
 2024-04-30 17:16:33 -07:00
Simon Ser
72ed71877c glapi: fix param type in TexGenxOES 
The spec [1] and _mesa_TexGenxOES both agree that it's GLfixed
instead of GLint.

[1]: https://registry.khronos.org/OpenGL/extensions/OES/OES_texture_cube_map.txt

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28825>
 2024-05-01 00:47:59 +02:00
Eric Engestrom
54258c1ee1 lavapipe/ci: skip another test that goes over the timeout 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28995>
 2024-04-30 22:51:03 +02:00
Eric Engestrom
0b739f7db8 lavapipe/ci: add the rest of the failures introduced by the 1.3.8.2 uprev 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28995>
 2024-04-30 22:51:03 +02:00
Eric Engestrom
c7d4b7a59c lavapipe/ci: drop fixed test from failures 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28995>
 2024-04-30 22:51:03 +02:00
Eric Engestrom
a963c67298 meson: use bool.to_int() instead of manually converting 
Suggested-by: @dbaker
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28990>
 2024-04-30 18:34:08 +00:00
Marek Olšák
f9d78f110c nir: add sleep intrinsics for AMD 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-By: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28889>
 2024-04-30 17:17:25 +00:00
Marek Olšák
b06a71b3cd nir: add streamout intrinsics for AMD GFX12 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-By: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28889>
 2024-04-30 17:17:25 +00:00
Marek Olšák
1a791c1303 nir: add nir_atomic_op_ordered_add_gfx12_amd 
for streamout

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-By: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28889>
 2024-04-30 17:17:25 +00:00
Marek Olšák
d4cfcbdde8 nir: add ACCESS_CP_GE_COHERENT_AMD 
required by amd gfx12

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-By: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28889>
 2024-04-30 17:17:25 +00:00
Eric Engestrom
7187373ec2 meson: always set USE_LIBGLVND 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28947>
 2024-04-30 16:22:50 +00:00
Eric Engestrom
21b527632e egl+glx: fix two #ifdef that should be #if like the rest 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28947>
 2024-04-30 16:22:50 +00:00
Eric Engestrom
11b060f41a meson: simplify -gsplit-dwarf compiler argument check 
Fixes: 44b080af07 ("meson: implement split-debug")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28898>
 2024-04-30 15:30:59 +00:00
Erik Faye-Lund
dd3ee08b05 docs/panfrost: link to conformant products 
Let's link to the conformant products page on the Khronos' website, in
case someone wants to look at some of the details of the submissions.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28968>
 2024-04-30 13:19:49 +00:00
Connor Abbott
fe4ebace79 ir3: Don't manually scalarize SSBO loads 
We call nir_lower_io_to_scalar already, so this should be dead code.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28949>
 2024-04-30 12:01:52 +00:00
Connor Abbott
cd15dec66e ir3: Don't scalarize all SSBO instructions 
Use the newly-introduced filter to only scalarize the instructions we
need to scalarize.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28949>
 2024-04-30 12:01:52 +00:00
Samuel Pitoiset
86281ef15f radv: add shaders BO to the cmdbuf BO list at bind time 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
 2024-04-30 07:18:08 +00:00
Samuel Pitoiset
42554e81b9 radv: add RT prolog BO to the cmdbuf BO list at bind time 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
 2024-04-30 07:18:08 +00:00
Samuel Pitoiset
42dc4b463b radv: add GS copy shader BO to the cmdbuf BO list at bind time 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
 2024-04-30 07:18:08 +00:00
Samuel Pitoiset
2664e058de radv: use the bound GS copy shader when emitting shader objects 
Similar but doesn't rely on shader_objs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
 2024-04-30 07:18:08 +00:00
Samuel Pitoiset
be98fe2724 radv: pre-compute VGT_TF_PARAM.DISTRIBUTION_MODE 
For less CPU overhead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
 2024-04-30 07:18:08 +00:00
Samuel Pitoiset
d7679c0370 radv: remove useless DB_Z_INFO.NUM_SAMPLES when emitting the MSAA state 
DB_Z_INFO.NUM_SAMPLES is now correctly set when a null framebuffer is
emitted and this is redundant.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
 2024-04-30 07:18:08 +00:00
Samuel Pitoiset
4dd682e227 radv: inline radv_get_pa_su_sc_mode_cntl() in radv_emit_culling() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
 2024-04-30 07:18:08 +00:00
Samuel Pitoiset
e651a2c856 radv: simplify radv_emit_primitive_restart_enable() 
Move emitting VGT_MULTI_PRIM_IB_RESET_INDX into the GFX6-8 branch.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
 2024-04-30 07:18:08 +00:00
Christian Gmeiner
d1e5b13359 mr-label-maker: Add teflon marker 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28959>
 2024-04-30 07:13:18 +00:00
Marek Olšák
8416ba9c25 amd/ci: 17 piglit failures are fixed for raven 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
 2024-04-30 06:47:21 +00:00
Marek Olšák
98e976dcdb radeonsi: check for FMASK correctly in gfx10_get_bin_sizes 
so that this code is skipped on gfx11+

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
 2024-04-30 06:47:21 +00:00
Marek Olšák
1a3c5cf17b radeonsi: enable DCC for MSAA on gfx10-10.3 
It improves performance of the MSAA resolving tests.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
 2024-04-30 06:47:21 +00:00
Marek Olšák
eb7d747651 radeonsi: add workarounds for DCC MSAA for gfx9-10 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
 2024-04-30 06:47:21 +00:00
Marek Olšák
1929bb0d8d radeonsi: validate IO semantics in scan_io_usage 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
 2024-04-30 06:47:21 +00:00
Marek Olšák
cfe197e61c radeonsi: fix KHR-GL46.texture_lod_bias.texture_lod_bias_all on gfx10-11 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
 2024-04-30 06:47:20 +00:00
Marek Olšák
6f09751548 radeonsi: don't invalidate L2 for internal compute without DCC stores 
When internal compute shaders are used, existing shader images are not
fully unbound, which means any image can be bound, even if the internal
shader doesn't use images.

This strengthens the code by applying it only to images used by internal
compute shaders.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
 2024-04-30 06:47:20 +00:00
Marek Olšák
c87ce78d10 ac/surface: enable thick tiling for 3D textures for better perf on gfx6-8 
This increases performance 2.5x for Viewperf/Energy on Tonga.
The value of thick_tiling is also fixed.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
 2024-04-30 06:47:20 +00:00
Marek Olšák
33f642aa09 ac/surface: disable DCC for 3D textures on gfx9 to improve performance 
This improves Viewperf/Energy perf by 60% on Vega10.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
 2024-04-30 06:47:20 +00:00
Marek Olšák
e05aec3fcd ac/gpu_info: set tcc_rb_non_coherent only if number of TCCs != number of RBs 
This sets it to false for Navi31 to eliminate unnecessary L2 cache
invalidations.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
 2024-04-30 06:47:20 +00:00
Iago Toral Quiroga
027c01bd8f v3d,v3dv: stop hard-coding max attrib divisor 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28964>
 2024-04-30 06:27:21 +00:00
Iago Toral Quiroga
e8f96dd0b0 v3dv: fix VK_KHR_vertex_attribute_divisor 
When this was promoted to EXT it expanded its properties struct to add a new
supportsNonZeroFirstInstance field.

Fixes: d38ff02c03 ("v3dv: mark some promoted extensions as supported")
Fixes: dEQP-VK.api.info.vulkan1p2_limits_validation.khr_vertex_attribute_divisor

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28964>
 2024-04-30 06:27:21 +00:00
Patrick Lerda
fe8fdc58db gallium/auxiliary/vl: fix typo which negatively impacts the src_stride initialization 
Note: As a matter of fact, this change by itself makes vdpau on r600 works again.
Indeed, r600 sets the stride value with vertex_buffer_index as the r600 index;
vertex_buffer_index was set to zero at the vl_compositor/init_buffers() stage on
the three elements. As a consequence of this typo the stride value was overwritten
to zero. This was breaking vdpau.

Fixes: 76725452 ("gallium: move vertex stride to CSO")
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10468
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10267
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28966>
 2024-04-30 05:45:21 +00:00