AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/brw: Use VEC for load_const

Browse Source 
This writes the whole destination register in a single builder call.
Eventually, VEC will write the whole destination register in one go,
allowing better visibility into how it is defined.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28971>
This commit is contained in:
Kenneth Graunke
2023-12-30 00:46:12 -08:00
parent 3c867bf2c7
commit d0a24496fd
1 changed files with 11 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/brw_fs_nir.cpp
+11 -8
View File
@@ -1934,31 +1934,32 @@ fs_nir_emit_load_const(nir_to_brw_state &ntb,
brw_type_with_size(BRW_TYPE_D, instr->def.bit_size);
fs_reg reg = bld.vgrf(reg_type, instr->def.num_components);
fs_reg comps[instr->def.num_components];
switch (instr->def.bit_size) {
case 8:
for (unsigned i = 0; i < instr->def.num_components; i++)
bld.MOV(offset(reg, bld, i), setup_imm_b(bld, instr->value[i].i8));
comps[i] = setup_imm_b(bld, instr->value[i].i8);
break;
case 16:
for (unsigned i = 0; i < instr->def.num_components; i++)
bld.MOV(offset(reg, bld, i), brw_imm_w(instr->value[i].i16));
comps[i] = brw_imm_w(instr->value[i].i16);
break;
case 32:
for (unsigned i = 0; i < instr->def.num_components; i++)
bld.MOV(offset(reg, bld, i), brw_imm_d(instr->value[i].i32));
comps[i] = brw_imm_d(instr->value[i].i32);
break;
case 64:
if (!devinfo->has_64bit_int) {
for (unsigned i = 0; i < instr->def.num_components; i++) {
bld.MOV(retype(offset(reg, bld, i), BRW_TYPE_DF),
brw_imm_df(instr->value[i].f64));
}
reg.type = BRW_TYPE_DF;
for (unsigned i = 0; i < instr->def.num_components; i++)
comps[i] = brw_imm_df(instr->value[i].f64);
} else {
for (unsigned i = 0; i < instr->def.num_components; i++)
bld.MOV(offset(reg, bld, i), brw_imm_q(instr->value[i].i64));
comps[i] = brw_imm_q(instr->value[i].i64);
}
break;
@@ -1966,6 +1967,8 @@ fs_nir_emit_load_const(nir_to_brw_state &ntb,
unreachable("Invalid bit size");
}
bld.VEC(reg, comps, instr->def.num_components);
ntb.ssa_values[instr->def.index] = reg;
}