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ac/gpu_info: set tcc_rb_non_coherent only if number of TCCs != number of RBs

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This sets it to false for Navi31 to eliminate unnecessary L2 cache
invalidations.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
This commit is contained in:
Marek Olšák
2024-04-15 02:27:52 -04:00
committed by Marge Bot
parent 027c01bd8f
commit e05aec3fcd
1 changed files with 2 additions and 1 deletions
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3
src/amd/common/ac_gpu_info.c
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@@ -1101,7 +1101,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->num_tcc_blocks = info->max_tcc_blocks;
}
info->tcc_rb_non_coherent = !util_is_power_of_two_or_zero(info->num_tcc_blocks);
info->tcc_rb_non_coherent = !util_is_power_of_two_or_zero(info->num_tcc_blocks) &&
info->num_rb != info->num_tcc_blocks;
if (info->drm_minor >= 52) {
info->sqc_inst_cache_size = device_info.sqc_inst_cache_size * 1024;