Alyssa Rosenzweig
0c2bbb470a
agx: Add agx_size_align_16 helper
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
9aeb5156bc
agx: Add typed move helper
...
Useful for u2u16 in lowering code.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
830d16e9f0
asahi: Add AGX_PUSH_ARRAY_SIZE_MINUS_1
...
Required to clamp array indices against the array sizes per the GLSL
spec. Metal also does this, implying it's required by the hardware for
correct operation.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
7b4ea2fd38
asahi: Implement texturing with non-zero start level
...
Unsure if this comes up anywhere.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
11072cfd21
asahi: Handle reloads of specific cube/mipfaces
...
The texture descriptor we construct for reloading needs to respect the
surface's texture/layer selection. Fix exactly the same bug as
b8c31ac06d ("lima: fix glCopyTexSubImage2D").
Fixes:
dEQP-GLES2.functional.texture.specification.basic_copytexsubimage2d.2d_rgb
dEQP-GLES2.functional.texture.specification.basic_copytexsubimage2d.2d_rgba
dEQP-GLES2.functional.texture.specification.basic_copytexsubimage2d.cube_rgb
dEQP-GLES2.functional.texture.specification.basic_copytexsubimage2d.cube_rgba
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
062ca49ca7
asahi: Add agx_map_texture_{cpu,gpu} helpers
...
Streamline access to particular layer/levels. These patterns show up
across the driver and are easy to screw up, so add a helper.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
a8bf729f8a
asahi: Support 2D array and 3D textures
...
As far as I can tell, these *must* be tiled. Other than that, the
implementation is completely routine. Passes
dEQP-GLES3.functional.texture.format.unsized.*2d_array*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
204e2ffe1b
asahi: Track mipmap state explicitly
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
e714fae263
asahi: Pass correct tile shift to tiling routines
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
5f10ffd6e2
asahi: Handle page alignment of miptrees
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
2c490cd4e3
asahi: Align linear texture's strides to 64 bytes
...
Required to pack the stride, and should improve cache performance.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
5d957011ff
asahi: Align allocations to effective tile size
...
May be smaller than 64x64.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
25f48996a6
asahi: Rename bpp to blocksize
...
Will matter for block compressed formats.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
856f64de24
asahi: Allow tiling of all bpps
...
Use the usual macro trick via Panfrost. Fixes textures with formats with
non-32-bit bpp, including:
dEQP-GLES2.functional.texture.specification.basic_teximage2d.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
2028873ef6
asahi: Dynamically configure tile size
...
We need to shrink the tile size when using small images (including
due to mipmapping) or when using large block sizes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
d103d64df6
asahi: Add some notes to XML about mipmapping
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
aea6d7f17f
asahi: Handle tiling of 2D arrays and 3D
...
Nothing special required, just need to respect the Z coordinate.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
06b2d97666
asahi: Add 2D Array and 3D texture dimensions
...
Add to XML and translate in the driver.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
266382d252
asahi: Respect mip level when rendering
...
Use hardware mip level field.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
1a3e21a4de
asahi: Identify Level field of render target descriptor
...
Hardware support for rendering into nonzero mip levels.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
65368d2f9a
asahi: Don't redefine MIN2/MAX2
...
The tiling function was written before the Mesa driver...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
570004175f
asahi: Streamline modifier selection
...
We can only use linear for 2D images, not even 2D arrays. Even for 2D
images, we only want to use linear if:
* We are required to use linear due to window system requirements.
* The texture is streaming.
Otherwise, we want to use tiled textures. (Or better, compressed, but we
don't support that yet.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903 >
2022-02-18 23:48:32 +00:00
Alyssa Rosenzweig
2d6233d04f
nir: Check all sizes in nir_alu_instr_is_comparison
...
nir_alu_instr_is_comparison needs to consider all comparison opcodes regardless
of size. Otherwise, they will be missed by nir_opt_move/sink.
Without this change, lowering booleans to integers regresses register
pressure (and spills/fills) significantly in certain shaders on Panfrost,
like android/com.miHoYo.GenshinImpact/1420.shader_test.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15073 >
2022-02-18 19:22:01 +00:00
Alyssa Rosenzweig
8f4b3c749e
pan/bi: Test avoiding FADD.v2f16 hazards in scheduler
...
There are many of them, and integration testing of the scheduler won't hit every
case. Add targeted unit tests for the various scheduling hazards of this funny
instruction.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15072 >
2022-02-18 16:15:04 +00:00
Alyssa Rosenzweig
9d95561c93
pan/bi: Test avoiding *FADD.v2f16 hazard in optimizer
...
This hazard exists but is obscure enough to be missed on our existing test
coverage (e.g the conformance tests). Add piles of unit tests for it.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15072 >
2022-02-18 16:15:04 +00:00
Alyssa Rosenzweig
24d2bdb1e0
pan/bi: Avoid *FADD.v2f16 hazard in scheduler
...
Obscure encoding restriction. Fixes crash (assertion fail when instruction
packing) in asphalt9/2659.shader_test on Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15072 >
2022-02-18 16:15:04 +00:00
Alyssa Rosenzweig
8e0eb592d5
pan/bi: Avoid *FADD.v2f16 hazard in optimizer
...
This is a very obscure encoding restriction in the Bifrost ISA. Unknown if any
real apps or tests hit this, but we still need to get it right sadly.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15072 >
2022-02-18 16:15:04 +00:00
Alyssa Rosenzweig
c2178d09d0
pan/va: Identify LEA_TEX_IMM table
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15069 >
2022-02-18 15:51:46 +00:00
Alyssa Rosenzweig
839f15259a
pan/va: Fix conservative branch handling
...
Mixed up lanes and conservative branch combine. Fix that.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15069 >
2022-02-18 15:51:46 +00:00
Alyssa Rosenzweig
81a9c857c8
pan/va: Make subgroup 4-bits
...
Future proofing.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15069 >
2022-02-18 15:51:46 +00:00
Alyssa Rosenzweig
9e851e75de
pan/va: Fix some units
...
Remove the todos.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15069 >
2022-02-18 15:51:46 +00:00
Alyssa Rosenzweig
47733ad1e1
pan/va: Parse units from the XML
...
We need this information for cycle counting in Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15069 >
2022-02-18 15:51:46 +00:00
Alyssa Rosenzweig
239d59ecdd
panvk: Don't use UBOs for meta_clear
...
It must always be pushed, so constructing a uniform remap table is
useless.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14913 >
2022-02-18 15:29:48 +00:00
Alyssa Rosenzweig
030dadb5f4
pan/mdg: Remove todo we'll probably never get to
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14888 >
2022-02-18 15:04:48 +00:00
Alyssa Rosenzweig
0e726d918f
pan/mdg: Assert that we don't see unknown jumps
...
I still don't understand why we don't see continues. But in case we do, scream
loudly so it can't be fixed.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14888 >
2022-02-18 15:04:48 +00:00
Alyssa Rosenzweig
8b70e7491a
pan/mdg: Delete dedicated fdot2 lowering
...
It's just lower_alu_to_scalar
total instructions in shared programs: 72542 -> 72528 (-0.02%)
instructions in affected programs: 673 -> 659 (-2.08%)
helped: 4
HURT: 1
helped stats (abs) min: 1.0 max: 11.0 x̄: 3.75 x̃: 1
helped stats (rel) min: 0.28% max: 6.79% x̄: 3.07% x̃: 2.60%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 3.03% max: 3.03% x̄: 3.03% x̃: 3.03%
95% mean confidence interval for instructions value: -8.65 3.05
95% mean confidence interval for instructions %-change: -6.32% 2.62%
Inconclusive result (value mean confidence interval includes 0).
total bundles in shared programs: 32051 -> 32036 (-0.05%)
bundles in affected programs: 207 -> 192 (-7.25%)
helped: 3
HURT: 0
helped stats (abs) min: 1.0 max: 10.0 x̄: 5.00 x̃: 4
helped stats (rel) min: 3.28% max: 13.89% x̄: 8.29% x̃: 7.69%
total quadwords in shared programs: 56496 -> 56487 (-0.02%)
quadwords in affected programs: 422 -> 413 (-2.13%)
helped: 2
HURT: 0
total registers in shared programs: 5106 -> 5104 (-0.04%)
registers in affected programs: 8 -> 6 (-25.00%)
helped: 1
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14888 >
2022-02-18 15:04:47 +00:00
Alyssa Rosenzweig
28cd2c9cca
pan/mdg: Delete stray comment
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14888 >
2022-02-18 15:04:47 +00:00
Alyssa Rosenzweig
eb0ef85cb6
pan/mdg: Clarify some ISA unknowns
...
Nothing usefully new here, just trying to improve signal:noise ratio on the
disassembly.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14888 >
2022-02-18 15:04:47 +00:00
Alyssa Rosenzweig
3a53e46fcd
pan/mdg: Handle 8/16-bit UBO loads
...
These will be seen by the compiler when we enable fp16 constant buffers.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14888 >
2022-02-18 15:04:47 +00:00
Alyssa Rosenzweig
8d949ecd3a
pan/mdg: Model zero/sign extension for 8/16-bit loads
...
The destinations are packed as if 32-bit even for 8/16-bit loads, so the mask
needs to be constructed accordingly.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14888 >
2022-02-18 15:04:47 +00:00
Alyssa Rosenzweig
ff970767a3
pan/mdg: Print optimized and scheduled shader
...
To help identify problems across the compiler, print more forms of the shader
with MIDGARD_MESA_DEBUG=shaders. Roughly matches the Bifrost compiler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14888 >
2022-02-18 15:04:47 +00:00
Alyssa Rosenzweig
b707dabbac
pan/mdg: Pull out skip_internal boolean
...
Aligns with Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14888 >
2022-02-18 15:04:47 +00:00
Jose Maria Casanova Crespo
90f966e05f
v3dv/v3d: Fix copyright holder to Raspberry Pi Ltd
...
Acked-by: Iago Toral Quiroga <itoral@igalia.com >
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15057 >
2022-02-18 11:50:07 +01:00
Kenneth Graunke
4ed9fd62c9
anv: Lower bufferImageGranularity to 1 from 64
...
The Vulkan 1.3 spec says:
"The implementation-dependent limit bufferImageGranularity specifies
a page-like granularity at which linear and non-linear resources
must be placed in adjacent memory locations to avoid aliasing. Two
resources which do not satisfy this granularity requirement are said
to alias. bufferImageGranularity is specified in bytes, and must be
a power of two. Implementations which do not impose a granularity
restriction may report a bufferImageGranularity value of one.
Note: Despite its name, bufferImageGranularity is really a
granularity between "linear" and "non-linear" resources."
We set this limit to 64 bytes (a cacheline) at the dawn of time, without
any real rationale attached. There shouldn't be any restrictions here.
Our tile sizes are typically 4K, and tiled resource addresses are
aligned to the tile size, and the extent is also a multiple of the tile
sized. So if a linear resource occurs before a tiled one, there will
naturally be some space due to the alignment of the tiled resource's
starting address. If a linear resource occurs after a tiled one, the
tiled resource's ending address is already 4K aligned, which is already
guaranteeing that they won't share a cacheline.
So I think it should be fine to reduce this to 1. The other Vulkan
driver for our hardware seems to advertise 1 here as well.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15066 >
2022-02-18 09:52:00 +00:00
Juan A. Suarez Romero
bfdb1064c5
vc4/ci: make piglit test mandatory
...
Make piglit test jobs to run always, as piglit testsuite offers more
coverage for the VC4 driver.
On the other hand, make the EGL testing manually, as we don't have
enough devices to execute all the tests fast enough.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com >
Acked-by: Iago Toral Quiroga <itoral@igalia.com >
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15045 >
2022-02-18 09:02:55 +00:00
Iago Toral Quiroga
750eeecf4e
broadcom/compiler: document that spill_base is used for spills and scratch
...
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15041 >
2022-02-18 08:38:19 +00:00
Iago Toral Quiroga
8883975209
broadcom/compiler: drop spill_count and add spilling boolean
...
We added spill_count to handle uniform batch spills, which we no longer do.
What we want now is a way to know if we are spilling registers.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15041 >
2022-02-18 08:38:19 +00:00
Iago Toral Quiroga
f3c3228522
broadcom/compiler: do not rebuild the interference graph after each spill
...
Instead, we only recompute liveness and we add new nodes and
interferences to the graph manually (we also need to patch
register classes in some cases).
To assist in this process, we also add an ip counter to our
instructions that we also recompute after each spill, which we use
to identify registers that cross thrsw boundries introduced with
TMU spills and fills and adjust their register classes accordingly
(removing their capacity to use accumulators).
This significantly reduces the CPU cost of spills. Using
shaders/closed/gputest/piano/7.shader_test as reference:
Compile time up to the first successful compile strategy in main is
~24s and with this change it is ~11s. With this speed up, we can now
try all 2-thread compile strategies (including the fallback scheduler)
in only ~15s.
A full shader-db run results in:
Total CPU time (seconds): 9904.67 -> 9087.98 (-8.25%)
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15041 >
2022-02-18 08:38:19 +00:00
Iago Toral Quiroga
59caaa7fb3
broadcom/compiler: reset spill/fill counts after lowering thread count.
...
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15041 >
2022-02-18 08:38:19 +00:00
Iago Toral Quiroga
92d819aaa0
broadcom/compiler: fix end of TMU sequence check
...
We may be pipelining TMU writes and reads, in which case we can
see both TMUWT and LDTMU at the end of a TMU sequence, so we should
not assume that a TMUWT always terminates a sequence.
Also, we had a bug where we were using inst instead of scan_inst
to check if we find another TMUWT after the curent instruction.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15041 >
2022-02-18 08:38:19 +00:00