asahi: Add agx_map_texture_{cpu,gpu} helpers

Streamline access to particular layer/levels. These patterns show up
across the driver and are easy to screw up, so add a helper.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903>

src/gallium/drivers/asahi/agx_pipe.c

@@ -237,16 +237,6 @@ agx_resource_create(struct pipe_screen *screen,
    return &nresource->base;
 }
 
-static uint8_t *
-agx_rsrc_offset(struct agx_resource *rsrc, unsigned level, unsigned z)
-{
-   struct agx_bo *bo = rsrc->bo;
-   uint8_t *map = ((uint8_t *) bo->ptr.cpu) + rsrc->slices[level].offset;
-   map += z * rsrc->array_stride;
-
-   return map;
-}
-
 static void
 agx_resource_destroy(struct pipe_screen *screen,
                      struct pipe_resource *prsrc)
@@ -312,7 +302,7 @@ agx_transfer_map(struct pipe_context *pctx,
 
       if ((usage & PIPE_MAP_READ) && BITSET_TEST(rsrc->data_valid, level)) {
          for (unsigned z = 0; z < box->depth; ++z) {
-            uint8_t *map = agx_rsrc_offset(rsrc, level, box->z + z);
+            uint8_t *map = agx_map_texture_cpu(rsrc, level, box->z + z);
             uint8_t *dst = (uint8_t *) transfer->map +
                            transfer->base.layer_stride * z;
 
@@ -336,7 +326,7 @@ agx_transfer_map(struct pipe_context *pctx,
       if ((usage & PIPE_MAP_WRITE) && (usage & PIPE_MAP_DIRECTLY))
          BITSET_SET(rsrc->data_valid, level);
 
-      return agx_rsrc_offset(rsrc, level, box->z)
+      return (uint8_t *) agx_map_texture_cpu(rsrc, level, box->z)
              + transfer->base.box.y * rsrc->slices[level].line_stride
              + transfer->base.box.x * blocksize;
    }
@@ -362,7 +352,7 @@ agx_transfer_unmap(struct pipe_context *pctx,
       assert(trans->map != NULL);
 
       for (unsigned z = 0; z < transfer->box.depth; ++z) {
-         uint8_t *map = agx_rsrc_offset(rsrc, transfer->level,
+         uint8_t *map = agx_map_texture_cpu(rsrc, transfer->level,
                transfer->box.z + z);
          uint8_t *src = (uint8_t *) trans->map +
                         transfer->layer_stride * z;

src/gallium/drivers/asahi/agx_state.c

@@ -480,7 +480,7 @@ agx_create_sampler_view(struct pipe_context *pctx,
       cfg.height = u_minify(texture->height0, level);
       cfg.levels = state->u.tex.last_level - level + 1;
       cfg.srgb = (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB);
-      cfg.address = rsrc->bo->ptr.gpu + rsrc->slices[level].offset;
+      cfg.address = agx_map_texture_gpu(rsrc, 0, state->u.tex.first_layer); // XXX: level?
       cfg.unk_mipmapped = rsrc->mipmapped;
       cfg.unk_2 = false;
 
@@ -749,7 +749,7 @@ agx_set_framebuffer_state(struct pipe_context *pctx,
          cfg.width = state->width;
          cfg.height = state->height;
          cfg.level = surf->u.tex.level;
-         cfg.buffer = tex->bo->ptr.gpu + layer * tex->array_stride;
+         cfg.buffer = agx_map_texture_gpu(tex, 0, layer);
 
          if (tex->mipmapped)
             cfg.unk_55 = 0x8;

src/gallium/drivers/asahi/agx_state.h

@@ -263,6 +263,28 @@ agx_resource(struct pipe_resource *pctx)
    return (struct agx_resource *) pctx;
 }
 
+/*
+ * Within a resource containing multiple layers and multiple mip levels,
+ * returns the offset from the start of the backing BO of a given level/slice.
+ */
+static inline uint32_t
+agx_texture_offset(struct agx_resource *rsrc, unsigned level, unsigned z)
+{
+   return rsrc->slices[level].offset + (z * rsrc->array_stride);
+}
+
+static inline void *
+agx_map_texture_cpu(struct agx_resource *rsrc, unsigned level, unsigned z)
+{
+   return ((uint8_t *) rsrc->bo->ptr.cpu) + agx_texture_offset(rsrc, level, z);
+}
+
+static inline uint64_t
+agx_map_texture_gpu(struct agx_resource *rsrc, unsigned level, unsigned z)
+{
+   return rsrc->bo->ptr.gpu + (uint64_t) agx_texture_offset(rsrc, level, z);
+}
+
 struct agx_transfer {
    struct pipe_transfer base;
    void *map;