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Author SHA1 Message Date
Mike Blumenkrantz
f75e886bf6 zink: only try update descriptors on draw/dispatch when necessary 
this call has a lot of overhead even if it does nothing

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37466>
 2025-09-18 17:58:08 +00:00
Mike Blumenkrantz
9d35a006ba zink: flag mesh pipeline_changed if switching from a shader object draw 
this otherwise might fail to do some updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37466>
 2025-09-18 17:58:08 +00:00
Mike Blumenkrantz
6f3d71f790 zink: flag gfx pipeline_changed if switching from a shader object draw 
this otherwise might fail to do some updates

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37466>
 2025-09-18 17:58:07 +00:00
Yiwei Zhang
951767ce36 intel/ds: update GPU clock to be sequence-scoped when applicable 
When CPU clock is the same with the authoritative trace clock (normally
default to CLOCK_BOOTTIME), perfetto drops the non-monotonic snapshots
to ensure validity of the global source clock in the resolution graph.
When they are different, the clocks are marked invalid and the rest of
the clock syncs will fail during trace processing.

There's no central daemon emitting consistent snapshots for
synchronization between CPU and GPU clocks on behalf of renderstages and
counters producers. The sequence-scoped clock (64 <= ID < 128) is unique
per producer + writer pair within the tracing session. So we can use
sequence-scoped clock for gpu clock whenever applicable, and fallback to
use global clock for dynamic minor allocated >= 192.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37425>
 2025-09-18 17:23:42 +00:00
Yiwei Zhang
7a1e952279 intel/ds: minor code clean up 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37425>
 2025-09-18 17:23:42 +00:00
Yiwei Zhang
7689aca21f intel/ds: simplify clock sync emit 
In short, perfetto doesn't require the initial clock snapshot to be
earlier than the timestamp to be converted. So we don't have to do
complex handling for it.

With this change:
- renderstage event requires clock sync, so we'd only emit clock
  snapshots on the traceq thread that handles the callbacks
- drops redundant sync_timestamp calls as well as sync_gpu_ts tracking
- no need to reset next_clock_sync_ns when tracing is disabled, since a
  snapshot is always emitted right after the initial interned data emit
  upon tracing start

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37425>
 2025-09-18 17:23:42 +00:00
Yiwei Zhang
7795669953 intel/ds: VulkanApiEvent doesn't rely on interning data 
The object name is part of the VkDebugUtilsObjectName event messages.
When the trace buffer is full and the ring buffer fill policy is chosen,
the debug obj events can be overwritten (lost), which is why we need the
RefreshSetDebugUtilsObjectNameEXT.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37425>
 2025-09-18 17:23:42 +00:00
Timur Kristóf
afc9e4ce8a docs: Add more details about the contribution process 
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37233>
 2025-09-18 17:00:12 +00:00
Olivia Lee
275ebde06d pan/va: fix bi_is_imm_desc_handle early return 
In the bi_emit_load_attr call site, we can use the imm_index value even
if the function returns false. The bifrost path handles this correctly.

Fixes: 652e1c2e13 ("pan/bi: Rework indices for attributes on Valhall")
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37464>
 2025-09-18 16:38:39 +00:00
Olivia Lee
d8b32f8980 panvk: pass correct variant shader/compile inputs to panvk_lower_nir 
Previously we were passing the original compile inputs, rather than the
variant-specific inputs. No actual bugs are caused by this because we
don't use the variant infrastructure for anything yet.

Fixes: ff9907927f ("panvk: Add basic infrastructure for shader variants")
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37463>
 2025-09-18 16:17:39 +00:00
Hans-Kristian Arntzen
3bc81ee6f1 radv/sqtt: Ensure that present fence gets signalled. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: 88cbe32048 ("radv: add support for RGP queue events")
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37438>
 2025-09-18 14:58:39 +00:00
Danylo Piliaiev
0908694f02 freedreno/decode: Fix preamble decoding 
Fixes: 46ad5a01a8 ("freedreno: Rename CP_SET_CTXSWITCH_IB to CP_SET_AMBLE")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37458>
 2025-09-18 14:44:33 +00:00
Alyssa Rosenzweig
804ced9047 intel: drop legacy flatshade handling 
Let mesa/st do the keying instead.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:11 +00:00
Alyssa Rosenzweig
36bd06ebab intel: drop clamp_fragment_color handling 
This is all dead code since we weren't even seting the cap in iris/crocus!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:11 +00:00
Alyssa Rosenzweig
957f326a10 brw: drop printf info plumbing 
unused since printf hashing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:10 +00:00
Alyssa Rosenzweig
58fd54b56e anv,hasvk: do not use unify_interfaces 
it's GLSL cruft we want to get rid of.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:10 +00:00
Alyssa Rosenzweig
bbf5bc8632 brw: cleanup int64 option set 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:09 +00:00
Alyssa Rosenzweig
168704c2fe brw: hoist shared options out of the stage loop 
ideally we'd have no stage switching, but this is just a cleanup for now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:09 +00:00
Alyssa Rosenzweig
0d7083d5bc brw: drop indirection on compiler options 
I see no point, we allocate for every shader stage anyway. This is a bit
simpler.

I'm not a fan of the brw_compiler singleton at all but torching that is not on
today's agenda. Flattening it a little bit very much is.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:08 +00:00
Alyssa Rosenzweig
2c161cc35d brw: drop unused brw_kernel code 
unused since we dropped GRL.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
 2025-09-18 14:14:07 +00:00
Alyssa Rosenzweig
c0c70cb392 nir/lower_flatshade: clean up 
while in the area.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37448>
 2025-09-18 13:37:03 +00:00
Rhys Perry
d6ed68212c aco: fix SGPR 8-bit nir_op_vec with mixed constant and non-constant 
For example, vec2(non_const, const)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 04e3d7ad93 ("aco: improve nir_op_vec with constant operands")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13911
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37405>
 2025-09-18 12:37:19 +00:00
Mary Guillemard
27f9e706f8 panvk: Properly set shader binary properties 
We do not support VK_EXT_shader_object so far but vk_shader layer
depends on those values so we should fill them.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37452>
 2025-09-18 10:41:50 +00:00
Mary Guillemard
e4fea2bc46 panvk: Follow nir_lower_io for subpass lowering 
We now set fb_fetch_output and fb_fetch_output_coherent to be consistent
with nir_lower_io.

This has no impact in general unless some generic pass depends on those
infos.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37452>
 2025-09-18 10:41:50 +00:00
Mary Guillemard
d9b11cd7a2 nir/print: Fix load_converted_output_pan and load_readonly_output_pan 
We were not printing IO infos properly for those intrinsics.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37452>
 2025-09-18 10:41:50 +00:00
Christian Gmeiner
2d8f8f82bd etnaviv: blt: Enable scissored clear 
The main challenge is handling tile status (TS) correctly. Full clears
simply mark tiles as "cleared" in TS metadata without touching pixels.
Scissored clears must first decompress existing TS tiles using the
current clear color, then apply the new color to the scissor region.

The implementation maintains the original surface clear color for TS
decompression operations while using the new color for actual clearing.
This prevents rendering artifacts when mixing BLT and 3D operations.

BLT engine operates directly with pixel positions and handles all TS
tile complexity automatically.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35956>
 2025-09-18 10:24:19 +00:00
Eric Engestrom
f2c4c5493e radv: add comment explaining why fp16 is disabled by default on gfx8 
Suggested-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37442>
 2025-09-18 09:08:21 +00:00
Eric Engestrom
1ee1e63bdb radv: make sure fp16 is enabled consistently on gfx8 
Fixes `dEQP-VK.api.info.vulkan1p4_limits_validation.general`

Fixes: f0f4ae1713 ("radv: Add radv_enable_float16_gfx8 drirc and enable for Indiana Jones TGC")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37442>
 2025-09-18 09:08:21 +00:00
Qiang Yu
faebbf9640 mesa: fix draw mesh shader indirect buffer size check 
We should not count the last draw command stride padding in
the indirect buffer.

Fixes: 176740c26f4 ("mesa: implement mesh shader draw calls")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37392>
 2025-09-18 01:38:08 +00:00
Chia-I Wu
85ec0fffa2 panvk: use common calibrated timestamp support 
It does not look like our custom version has anything special to offer.

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37421>
 2025-09-17 22:55:23 +00:00
Chia-I Wu
e9444b28fd panvk: require gpu_can_query_timestamp for calibrated timestamps 
Advertise the extensions without VK_TIME_DOMAIN_DEVICE_KHR support is
not very useful.

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37421>
 2025-09-17 22:55:23 +00:00
Paulo Zanoni
25d26a89e3 isl: allow sparse with STC_CCS on DG2 
Thanks to Nanley Chery for pointing out this possibility.

v2: Make it simpler (Nanley).

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37419>
 2025-09-17 21:42:58 +00:00
Paulo Zanoni
7dd66d6bb1 isl: allow sparse with CCS on Xe2 and newer 
When the auxiliary surface is handled by the hardware directly,
there's nothing to bind besides the main pixels, so we can allow
sparse without doing anything else. We can't do this in the exact same
way with DG2 (which has_flat_ccs) because it uses the
aux_state_tracking_buffer.

v2: Fix spelling (Nanley).

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37419>
 2025-09-17 21:42:58 +00:00
Paulo Zanoni
e7fd99c205 intel: rework the way sparse forces CCS/MCS/HIZ to be disabled 
We want to be a little more granular than just "aux surfaces are
completely incompatible with sparse!", so have each of
isl_surf_get_*_surf disable itself when sparse is used.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37419>
 2025-09-17 21:42:58 +00:00
Gert Wollny
3b3c3ccf56 nir+r600: add option to avoid contracting fabs into ffma 
On r600 ternary operations can't use the fabs source modifier, so
converting "fadd(fabs(fmul(a, b), c)" to  "ffma(fabs(a), fabs(b), c)"
adds one more instruction in the backend, hence avoid this.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37440>
 2025-09-17 21:03:58 +00:00
Christian Gmeiner
a7d2570296 nir/opt_algebraic: optimize f2i32(fround_even(x)) to f2i32_rtne(x) 
Add late optimization to fuse f2i32 and fround_even operations into a
single f2i32_rtne instruction when the intermediate fround_even result
is only used once. This eliminates redundant rounding since f2i32_rtne
performs round-to-nearest-even conversion directly.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Tested-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37426>
 2025-09-17 20:31:59 +00:00
Emma Anholt
0f320b7a1d d3d10umd: Add missing dependency on u_formats codegen. 
Fixes this error during Shader.cpp build:

..\src\util/format/u_formats.h(33): fatal error C1083: Cannot open include file: 'util/format/u_format_gen.h': No such file or directory

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37316>
 2025-09-17 12:04:37 -07:00
Emma Anholt
114e6a3104 ir3: Use a linear allocation context for ir3_instructions. 
Again, instrs don't get freed as we go, so the linear gc context saves us
5 pointers per instr.

Fossil replay time for deadspace3 on a debugoptimized build -4.85258% +/-
3.04009% (n=10)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37316>
 2025-09-17 12:02:47 -07:00
Emma Anholt
12fae29ec2 ir3: Use a linear allocation context for ir3_registers. 
Since we don't free registers as we go, we can just allocate them in a
linear gc context that gets freed at ralloc destroy.  Saves 5 pointers of
memory per register for the ralloc overhead.

Fossil replay time for deadspace3 on a debugoptimized build -4.30353% +/-
1.80078% (n=10).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37316>
 2025-09-17 12:02:47 -07:00
Emma Anholt
1b4c2c1566 ir3: Use a bitset for the defs-seen table. 
Fossil reply time for deadspace3 on a debugoptimized build -3.20856% +/-
1.48994% (n=15).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37316>
 2025-09-17 12:02:47 -07:00
Eric Engestrom
144879ca40 doc/features.txt: add missing supported dzn extensions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37404>
 2025-09-17 16:09:29 +00:00
Eric Engestrom
102017f2ca docs: add sha sum for 25.2.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37446>
 2025-09-17 16:04:42 +00:00
Eric Engestrom
d816a0eb2a docs: add release notes for 25.2.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37446>
 2025-09-17 16:04:42 +00:00
Eric Engestrom
b0171edda7 docs: update calendar for 25.2.3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37446>
 2025-09-17 16:04:42 +00:00
Icenowy Zheng
44aa7cfb4f pvr: implement samplerAnisotropy 
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36242>
 2025-09-17 15:44:32 +00:00
Dylan Baker
209deff350 calendar: Update release dates and change 25.3 to Dylan 
We'll pull the calendar in to regularly scheduled time, and then cut a
couple of 25.2 releases we shouldn't need.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37443>
 2025-09-17 15:39:14 +00:00
Karmjit Mahil
9c6183604f nir, ir3: Add lower_fmulz_with_abs_min backend option 
This commits adds the `lower_fmulz_with_abs_min` which lowers
`fmulz` -> `min(abs(a), abs(b)) == 0.0 ? 0.0 : a * b`
`ffmaz` -> `min(abs(a), abs(b)) == 0.0 ? c : ffma(a, b, c)

This is useful for ISAs which have `abs` for free on `min` such as
ir3.

Adreno A750 Benchmark of 10 runs of 5 DX9 single frame trimmed
captures looped 2048 times using u_trace measuring
`start_render_pass` to `end_render_pass` results:

sysmem:
-1.91156%, -2.21791%, -2.02533%, -2.21666%, -2.33272%,
-2.67349%, -1.75278%, -2.05923%, -2.26892%, -2.10506%
Avg:  ~ -2.16%
ST.S: ~  0.25%

gmem:
-3.61496%, -3.66682%, -3.80901%, -3.51198%, -3.72950%,
-3.71413%, -3.64467%, -3.67092%, -3.90640%, -3.83888%
Avg:  ~ -3.71%
ST.S: ~  0.12%

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31479>
 2025-09-17 15:02:50 +00:00
Karmjit Mahil
8d19ffef0a nir: Add more matches for fmulz 
In some cases after other passes, `(a == 0.0 ? 0 : b)` can be
turned into `(a != 0.0 ? b : 0)`, so let's match those cases too.

Also matching `min(abs(a), abs(b)) == 0.0 ? 0.0 : a * b`.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31479>
 2025-09-17 15:02:50 +00:00
Mike Blumenkrantz
c85168160e zink: reset batch states on destroy 
these may otherwise have been in the reset queue and thus contain
resource refs

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37379>
 2025-09-17 10:00:26 -04:00
Mike Blumenkrantz
2330839641 zink: null out zink_batch_state::ctx when adding to the screen list 
this otherwise leaves a dangling pointer

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37379>
 2025-09-17 10:00:25 -04:00