f5fe81daea
gallium/radeon: Fix losing holes when allocating virtual address space.
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If a hole exactly matches the allocated size plus alignment, we would fail to
preserve the alignment as a hole. This would result in never being able to use
the alignment area for an allocation again.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
2012-08-16 11:58:23 +02:00
206d07625c
gallium/radeon: Merge holes when freeing virtual address space.
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Otherwise we'll likely end up with an ever increasing amount of ever smaller
holes.
Requires keeping the list ordered wrt offsets.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
2012-08-16 09:39:36 +02:00
c25968f3e2
gallium/radeon: Make va_offset 64 bits wide.
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Otherwise we'd wrap around after 32 bits. The kernel currently limits GPU
virtual address space to 4GB anyway, but that will probably change sooner or
later, and this would result in confusing error messages when running out of
virtual address space even now.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
2012-08-16 09:37:33 +02:00
1597176f70
llvmpipe: Silence Coverity incorrect sizeof expression defect.
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Signed-off-by: Vinson Lee <vlee@freedesktop.org >
Reviewed-by: José Fonseca <jfonseca@vmware.com >
2012-08-15 22:15:49 -07:00
3d6892c479
scons: Add option to enable floating-point textures.
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Signed-off-by: Vinson Lee <vlee@freedesktop.org >
Reviewed-by: José Fonseca <jfonseca@vmware.com >
2012-08-15 22:04:24 -07:00
6a3ac03f2b
glx/dri2: add dri2 prime support.
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This adds support for having libGL pick a different driver for prime support.
DRI_PRIME env var is set to the value retrieved from the server randr
provider calls, by the calling process. (generally DRI_PRIME=1 will be
the right answer).
Signed-off-by: Dave Airlie <airlied@redhat.com >
2012-08-16 10:02:10 +10:00
565a4e2a86
radeon/llvm: Enable if-cvt
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Signed-off-by: Tom Stellard <thomas.stellard@amd.com >
2012-08-15 21:07:14 +00:00
a614979286
radeon/llvm: Add callbacks needed by if-cvt
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Signed-off-by: Tom Stellard <thomas.stellard@amd.com >
2012-08-15 21:07:14 +00:00
0eca5fd919
radeon/llvm: Lower branch/branch_cond into predicated jump
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Signed-off-by: Tom Stellard <thomas.stellard@amd.com >
2012-08-15 21:07:14 +00:00
6db2e9fdb0
radeon/llvm: Add a predicated JUMP instruction
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Signed-off-by: Tom Stellard <thomas.stellard@amd.com >
2012-08-15 21:07:13 +00:00
8263408a91
radeon/llvm: Support for predicate bit
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Tom Stellard:
- A few changes to predicate register defs
Signed-off-by: Tom Stellard <thomas.stellard@amd.com >
2012-08-15 21:07:13 +00:00
8f597d57e9
r600g: Glue to handle predicate aware output from llvm
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Signed-off-by: Tom Stellard <thomas.stellard@amd.com >
2012-08-15 21:07:13 +00:00
72f7632c6b
r600g: Fix instruction group merge when there are predicated insts.
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Signed-off-by: Tom Stellard <thomas.stellard@amd.com >
2012-08-15 21:07:13 +00:00
56227f875b
radeon/llvm: Do not use PV/PS if PRED_SEL does not match
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Signed-off-by: Tom Stellard <thomas.stellard@amd.com >
2012-08-15 21:07:13 +00:00
da676eab93
r600g: Add support for predicates
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Signed-off-by: Tom Stellard <thomas.stellard@amd.com >
2012-08-15 21:07:13 +00:00
cf76edd300
radeonsi: move ps sampler state into PM4 stream
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Signed-off-by: Christian König <deathsimple@vodafone.de >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
2012-08-15 22:13:19 +02:00
ec5b698525
radeonsi: move ps sampler views into PM4 stream
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Signed-off-by: Christian König <deathsimple@vodafone.de >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
2012-08-15 22:13:19 +02:00
54de6f452c
radeonsi: move vertex state descriptors into PM4 stream
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Signed-off-by: Christian König <deathsimple@vodafone.de >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
2012-08-15 22:13:19 +02:00
f2c95d93db
radeonsi: add shader data infrastructure
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With this we can embed data for the shaders (like resource
descriptors) into the PM4 stream.
Signed-off-by: Christian König <deathsimple@vodafone.de >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
2012-08-15 22:13:19 +02:00
4444b9d1ec
radeon/llvm: add support to fetch temps as vectors
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Necessary for texture fetches with temp regs as source on SI.
Signed-off-by: Christian König <deathsimple@vodafone.de >
Reviewed-by: Tom Stellard <thomas.stellard@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
2012-08-15 22:13:19 +02:00
b6051bc785
radeon/llvm: Remove AMDGPUUtil.cpp
2012-08-15 18:35:26 +00:00
040c2e0456
radeon/llvm: Cleanup AMDGPUUtil.cpp
2012-08-15 18:35:25 +00:00
3aaa209293
radeon/llvm: Lower loads from USE_SGPR adddress space during DAG lowering
2012-08-15 18:35:25 +00:00
40c41fe890
radeon/llvm: Add live-in registers during DAG lowering
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Psuedo instructions emulating live-in registers have been removed
and their corresponding intrinsics are now being lowered during DAG
lowering.
2012-08-15 18:35:25 +00:00
f3480f9234
radeon/llvm: Lower store_output intrinsic during DAG lowering
2012-08-15 18:35:25 +00:00
a76a0f7422
radeon/llvm: Force VTX_READ instructions to use same reg for src and dst
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I was seeing some GPU hangs that seemed to be cause by ALU instructions
writing to the same register used as the source for VTX_READ. Adding
this constraint to the VTX_READ instructions avoids this situation.
2012-08-15 18:35:25 +00:00
97b4b97b2f
radeonsi: fix build breakage after u_blitter changes
2012-08-15 20:03:37 +02:00
e0cc61bd91
gallium/u_blitter: document custom meta helpers
2012-08-15 19:20:58 +02:00
b3b5bb9ddb
r600g: disable handling of DISCARD_RANGE
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https://bugs.freedesktop.org/show_bug.cgi?id=53130
2012-08-15 19:20:58 +02:00
44f14ebd7b
r600g: implement timestamp query and get_timestamp hook
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
2012-08-15 19:20:58 +02:00
1932bc8aae
r600g: enable MSAA on evergreen by default
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v2: add the DRM version check
2012-08-15 19:20:58 +02:00
870af19d70
r600g: implement copying between MSAA textures
2012-08-15 19:20:58 +02:00
0f86915c53
r600g: implement MSAA color resolve
2012-08-15 19:20:58 +02:00
94b634eca0
r600g: implement MSAA depth-stencil decompression and resolve
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and integer textures, which are resolved the same as depth, I think.
2012-08-15 19:20:58 +02:00
6d3ad2dd2b
r600g: implement TXQ_LZ opcode
2012-08-15 19:20:57 +02:00
4b78df9c81
r600g: implement MSAA rendering and texturing for evergreen and cayman
2012-08-15 19:20:57 +02:00
a01791add0
r600g: implement set_sample_mask
2012-08-15 19:20:57 +02:00
6517225078
r600g: implement alpha-to-coverage
2012-08-15 19:20:57 +02:00
26cb887ea2
r600g: implement alpha-to-one
2012-08-15 19:20:57 +02:00
4f21595276
r600g: remove support for 3-channel colorbuffers
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We have no sampler support for them.
2012-08-15 19:20:57 +02:00
2f14202f52
configure.ac: bump libdrm_radeon requirement to 2.6.38
2012-08-15 19:20:57 +02:00
a7f4d3b740
winsys/radeon: print error if CS is overflowed
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and don't submit the CS to the kernel.
2012-08-15 19:20:57 +02:00
dc5e61d884
gallium/u_blitter: implement X and Y texture flipping
2012-08-15 19:20:57 +02:00
825b45366d
gallium/u_blitter: implement blitting multisample resources
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It can blit only one sample at a time (it should be called in a loop).
2012-08-15 19:20:57 +02:00
dacf5dc9ac
gallium: add TGSI support for multisample textures
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The only allowed instructions are TXQ_LZ and TXF.
TXQ_LZ is like TXQ, but without the LOD parameter (which is always zero
with MSAA textures)
The 3rd or the 4th texcoord component in TXF should contain the sample index
for a 2D_MSAA or 2D_ARRAY_MSAA texture, respectively.
2012-08-15 19:20:57 +02:00
ba53573a8b
gallium/tgsi: fix TGSI text parser
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The problem was that the string matching succeeded e.g. for "2D" when there
was actually "2D_MSAA" and then failed parsing "_MSAA".
To prevent similar failures in the future, let's fix this kind of error
everywhere.
2012-08-15 19:20:57 +02:00
b7c4ee21c5
gallium/u_blit: set dst format from pipe_resource, not pipe_surface
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We use it to decide whether we can use resource_copy_region.
NOTE: This is a candidate for the 8.0 branch.
2012-08-15 19:20:57 +02:00
1a17c42344
gallium: make pipe_box signed in order to represent flipped blits
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This will be used by u_blitter.
2012-08-15 19:20:57 +02:00
03b78ceb50
st/mesa: don't clamp fragment color with integer colorbuffer
2012-08-15 19:20:57 +02:00
e06d6168cb
mesa: flush vertices in test_framebuffer_completeness
2012-08-15 19:20:57 +02:00
Michel Dänzer