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Author SHA1 Message Date
Valentine Burley
f35c5cfabb ci/fluster: Uprev Fluster 
JVT-SVC_V1 was renamed to JVT-SVC upstream.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35880>
 2025-08-14 07:25:09 +00:00
Iván Briano
35190aac91 anv: dirty descriptor state on CmdSetDescriptorBufferOffets 
Calling vkCmdBindDescriptorBuffersEXT() does not invalidate previously
set descriptor sets. Move the state dirtying to
vkCmdSetDescriptorBufferOffets.

Fixes: ab7641b8dc ("anv: implement descriptor buffer binding")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36768>
 2025-08-14 07:05:31 +00:00
Iván Briano
382b8e3aa2 anv: check for pending_db_mode when dirtying descriptor mode 
If an application switches back and forth between descriptor sets and
descriptor buffers before executing a draw/dispatch, we could end up in
a wrong state due to pending_db_mode not getting updated.

Fixes: ab7641b8dc ("anv: implement descriptor buffer binding")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36768>
 2025-08-14 07:05:31 +00:00
Samuel Pitoiset
0ac7f1888f radv: reduce the combined image/sampler desc size on GFX11+ 
From 96 to 64 due to the 32 bytes descriptor alignment.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36762>
 2025-08-14 06:47:30 +00:00
Samuel Pitoiset
897201d710 radv: only write 32 bytes for combined image/sampler on GFX11+ 
It should be slightly more optimal.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36762>
 2025-08-14 06:47:30 +00:00
Samuel Pitoiset
b6d093c4f5 radv: do not hardcode the combined image/sampler offset in the db path 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36762>
 2025-08-14 06:47:30 +00:00
Samuel Pitoiset
f2b5446cc4 radv: use radv_write_sampler_descriptor() for combined image/sampler 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36762>
 2025-08-14 06:47:29 +00:00
Samuel Pitoiset
3fb33aada6 radv: optimize the preprocess buffer size for DGC IES compute 
Using the precomputed information.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
 2025-08-14 06:25:49 +00:00
Samuel Pitoiset
e527d2d801 radv: pre-compute more information when updating DGC IES 
These information need to consider that pipelines/shaders in the same
IES struct might slightly differ. They will be used to determine the
preprocess buffer size in a better way.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
 2025-08-14 06:25:49 +00:00
Samuel Pitoiset
0db165ebda radv: pass the IES struct when computing the DGC sequence size 
I completely missed that it's required for the application to pass the
IES struct in vkGetGeneratedCommandsMemoryRequirementsEXT. Also any
changes to the IES struct requires to call it again.

This will allow us to do more optimizations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
 2025-08-14 06:25:49 +00:00
Samuel Pitoiset
771d4b55e8 radv: remove redundant push constant size alignment for DGC 
It's already aligned to 16 bytes when the pipeline layout is created.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
 2025-08-14 06:25:48 +00:00
Samuel Pitoiset
3359386145 radv: fix reserving space for emitting push constants with DGC IES 
layout->push_constant_mask is only the DGC push constant mask (ie. the
tokens that are specified), but with IES all push constants are emitted
from the DGC shader. So it should be the total range of push constant.

This used to work by luck due to the preprocess buffer alignment.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
 2025-08-14 06:25:48 +00:00
Job Noorman
23c49ede57 ir3: use isam for txf with LOD 0 
isaml with LOD 0 is equivalent to isam. Use isam if possible because it
needs one less src register.

Totals:
Instrs: 49141575 -> 49109622 (-0.07%); split: -0.07%, +0.00%
CodeSize: 102938312 -> 102865138 (-0.07%)
NOPs: 8464238 -> 8463245 (-0.01%); split: -0.02%, +0.01%
(ss)-stall: 4013710 -> 4014037 (+0.01%); split: -0.00%, +0.01%
(sy)-stall: 16712850 -> 16712860 (+0.00%)
Preamble Instrs: 11120034 -> 11119863 (-0.00%)
Last helper: 11942609 -> 11934226 (-0.07%); split: -0.07%, +0.00%
Cat0: 9320007 -> 9319014 (-0.01%); split: -0.02%, +0.01%
Cat7: 1636810 -> 1605850 (-1.89%)

Totals from 9523 (5.78% of 164705) affected shaders:
Instrs: 7755614 -> 7723661 (-0.41%); split: -0.41%, +0.00%
CodeSize: 15214510 -> 15141336 (-0.48%)
NOPs: 1722109 -> 1721116 (-0.06%); split: -0.11%, +0.05%
(ss)-stall: 807953 -> 808280 (+0.04%); split: -0.00%, +0.04%
(sy)-stall: 3054163 -> 3054173 (+0.00%)
Preamble Instrs: 1653169 -> 1652998 (-0.01%)
Last helper: 2333301 -> 2324918 (-0.36%); split: -0.36%, +0.00%
Cat0: 1888236 -> 1887243 (-0.05%); split: -0.10%, +0.05%
Cat7: 276671 -> 245711 (-11.19%)

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36766>
 2025-08-14 04:47:02 +00:00
Yonggang Luo
fc1b26f4dc aco: Fixes warning note: ambiguity is between a regular call to this operator and a call with the argument order reversed 
../../src/amd/compiler/aco_util.h:300:9: note: ambiguity is between a regular call to this operator and a call with the argument order reversed
  300 |    bool operator==(const monotonic_buffer_resource& other) { return buffer == other.buffer; }

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36722>
 2025-08-13 19:49:37 +00:00
Emma Anholt
acf226f3a7 tu: Fix the comment about DRM_CAP_SYNCOBJ_TIMELINE support. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36563>
 2025-08-13 18:57:43 +00:00
Emma Anholt
00336bc9c4 tu: Use the common syncobj sync type for the layered timelines. 
Everyone else doing emulated timelines is doing it on top of their base
binary type, and that appears to have been the intent of the shared
emulation layer.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36563>
 2025-08-13 18:57:43 +00:00
Emma Anholt
9e61e72e9f vk/runtime: Set GPU_MULTI_WAIT on the drm syncobj type. 
DRM syncobjs always let you wait repeatedly on them, so we can set the
flag in the core instead of having each driver override it once they try
to enable the emulated timeline semaphores.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36563>
 2025-08-13 18:57:42 +00:00
Lorenzo Rossi
7375dfd56d nak/kepler: Refine instruction scheduling 
Previously some KeplerA chips failed various dEQP tests when instruction
scheduling was enabled.
In particular, `memory_model.message_passing` had issues where a
`membar` instruction canceled some in-flight predicate writes, and
`barrier.write_image_tess_control_read_image_compute.image_128_r32_uint`
had issues around the `Cont` instruction.

This patch refines instruction scheduling to better match the output of
nvcc. Fixing the various dEQP failing tests.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13528
Fixes: c35990c4bc ("nak: Add real instruction dependencies for Kepler")
Signed-off-by: Lorenzo Rossi <snowycoder@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36393>
 2025-08-13 18:39:56 +00:00
Tapani Pälli
42088cd602 isl/blorp: handle failing 96bpp linear blit case 
Fix the aux usage assert in blorp for 96bpp linear blit and provide CMF
values for RGB formats supported by isl_format_rgb_to_rgba.

CC: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13670
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36709>
 2025-08-13 16:09:12 +00:00
Karol Herbst
7251c8121b nak: support bra.u with a upred source on Ampere and newer 
CodeSize: 934788544 -> 924393088 (-1.11%); split: -1.11%, +0.00%
Number of GPRs: 3537163 -> 3537161 (-0.00%)
SLM Size: 840556 -> 840560 (+0.00%)
Static cycle count: 222856984 -> 217707273 (-2.31%); split: -2.31%, +0.00%
Spills to memory: 56645 -> 56648 (+0.01%)
Fills from memory: 56645 -> 56648 (+0.01%)
Spills to reg: 67982 -> 68532 (+0.81%); split: -0.02%, +0.83%
Fills from reg: 80336 -> 80547 (+0.26%); split: -0.03%, +0.29%
Max warps/SM: 3666696 -> 3666700 (+0.00%)

Totals from 33243 (37.94% of 87622) affected shaders:
CodeSize: 666331984 -> 655936528 (-1.56%); split: -1.56%, +0.00%
Number of GPRs: 1739764 -> 1739762 (-0.00%)
SLM Size: 588164 -> 588168 (+0.00%)
Static cycle count: 168348730 -> 163199019 (-3.06%); split: -3.06%, +0.00%
Spills to memory: 56502 -> 56505 (+0.01%)
Fills from memory: 56502 -> 56505 (+0.01%)
Spills to reg: 55951 -> 56501 (+0.98%); split: -0.03%, +1.01%
Fills from reg: 65060 -> 65271 (+0.32%); split: -0.03%, +0.36%
Max warps/SM: 1246864 -> 1246868 (+0.00%)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36465>
 2025-08-13 15:46:59 +00:00
Karol Herbst
b79e55bed7 nak: relayout opt_uniform_instrs 
I'm touching this code in the next commit, so this makes it easier to
review.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36465>
 2025-08-13 15:46:59 +00:00
Karol Herbst
96f2348bdf nak: add more helpers for predicates 
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36465>
 2025-08-13 15:46:59 +00:00
Karol Herbst
475c8f0580 nak: set max_gpr to multiple of 8s 
Optimizations cutting down on GPRs often lead to the akward situations
where RA being more restricted and having to insert more mov instructions
pumping up the instruction counts.

In order to give developers more reliable stats we just set the max_gprs
to the next multiple of 8 including taking hw reserved registers into
account.

This does not impact occupancy in any way despite the increase in gprs.

Totals:
CodeSize: 920980864 -> 914748784 (-0.68%); split: -0.69%, +0.02%
Number of GPRs: 3544248 -> 3879749 (+9.47%)
Static cycle count: 217345431 -> 216414194 (-0.43%); split: -0.50%, +0.07%

Totals from 78493 (89.58% of 87622) affected shaders:
CodeSize: 795883088 -> 789651008 (-0.78%); split: -0.80%, +0.02%
Number of GPRs: 3108571 -> 3444072 (+10.79%)
Static cycle count: 187450578 -> 186519341 (-0.50%); split: -0.58%, +0.08%

Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36514>
 2025-08-13 15:29:43 +00:00
Eric Engestrom
708e2edc23 llvmpipe/ci: consistently use x11- prefix for deqp-egl-x11 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36759>
 2025-08-13 15:12:31 +00:00
Eric Engestrom
8a2bf596aa iris/ci: consistently use x11- prefix for deqp-egl-x11 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36759>
 2025-08-13 15:12:31 +00:00
Eric Engestrom
1695328512 freedreno/ci: consistently use x11- prefix for deqp-egl-x11 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36759>
 2025-08-13 15:12:31 +00:00
Eric Engestrom
0a8effb054 docs: add sha sum for 25.1.8 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36761>
 2025-08-13 15:07:23 +00:00
Eric Engestrom
64d43e4148 docs: add release notes for 25.1.8 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36761>
 2025-08-13 15:07:23 +00:00
Eric Engestrom
4f5e3aeb0f docs: update calendar for 25.1.8 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36761>
 2025-08-13 15:07:23 +00:00
Valentine Burley
e4933d1d90 zink/ci: Document recent flakes on TGL 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36409>
 2025-08-13 14:48:32 +00:00
Valentine Burley
4ba1128600 zink/ci: Add EGL coverage on lavapipe 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36409>
 2025-08-13 14:48:32 +00:00
Valentine Burley
72af71a17a zink/ci: Run full zink-lavapipe job pre-merge 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36409>
 2025-08-13 14:48:32 +00:00
Yonggang Luo
67385aba94 ci/windows: Enable virgl for MSVC 
Guard virgl to be compiled with MSVC

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36726>
 2025-08-13 14:22:19 +00:00
Yonggang Luo
e54d5c9c13 virgl: Fixes differs in parameter lists 
../src/gallium/drivers/virgl/virgl_context.c(1783): error C2220: the following warning is treated as an error
../src/gallium/drivers/virgl/virgl_context.c(1783): warning C4113: 'void (__cdecl *)(pipe_context *,pipe_fence_handle **,pipe_flush_flags)' differs in parameter lists from 'void (__cdecl *)(pipe_context *,pipe_fence_handle **,unsigned int)'

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36726>
 2025-08-13 14:22:19 +00:00
Yonggang Luo
671bd2d7da virgl: Fixes warning: cast to smaller integer type 'unsigned long' from 'void *' [-Wvoid-pointer-to-int-cast] 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36726>
 2025-08-13 14:22:19 +00:00
Corentin Noël
f78a52fd0a tgsi: Drop TGSI_SEMANTIC_TESS_DEFAULT_OUTER/INNER_LEVEL 
Nothing is emitting this anymore and it is not used by virglrenderer too.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36758>
 2025-08-13 13:55:01 +00:00
Yonggang Luo
e14a9e7fe4 util: Remove dbghelp.h that already comes with winsdk and mingw for fix warning with mingw 
The warning is:
../../src/util/dbghelp.h:900:10: warning: the current #pragma pack alignment value is modified in the included file [-Wpragma-pack]
  900 | #include <pshpack4.h>

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36708>
 2025-08-13 13:18:52 +00:00
Roland Scheidegger
67b90113a6 llvmpipe: Fix wrong GS invocation count when using instanced GS 
Each invocation obviously counts toward the total GS invocation count.

Reviewed-by: Brian Paul <brian.paul@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36686>
 2025-08-13 12:52:42 +00:00
Lionel Landwerlin
c871a62a75 brw: move URB channel mask shifting to the lowering pass 
For example Xe2 uses the LSC and doesn´t need the shifting, so let's
just apply it where it's needed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36757>
 2025-08-13 12:01:49 +00:00
Lionel Landwerlin
99cf8273f6 anv: stop using descriptor layouts for descriptor buffers push sizes 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36757>
 2025-08-13 12:01:49 +00:00
Lionel Landwerlin
68838d7001 brw: reorder reloc enums to leave embedded samplers at the end 
So that the driver can allocate an array of relocations using
BRW_SHADER_RELOC_EMBEDDED_SAMPLER_HANDLE + number_of_embedded_samplers

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36757>
 2025-08-13 12:01:49 +00:00
Lionel Landwerlin
69a04151db vulkan/runtime: add ray tracing pipeline support 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36757>
 2025-08-13 12:01:49 +00:00
Lionel Landwerlin
daac500e98 vulkan/runtime: add a few more shader properties 
Ray tracing pipelines can contain unlimited number of shaders unlike
compute/graphics ones. Having the driver finding the maximum
scratch/ray-query/stack usage can be time consumming when this can be
stored on the pipeline and the runtime tell the driver at bind time.

These fields are unused for other shaders and so drivers can ignore
them.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36757>
 2025-08-13 12:01:49 +00:00
Yonggang Luo
c321f61c21 microsoft/compiler: Fixes dxcapi.h compiling warning with mingw64-clang 
The warning is:
dxcapi.h:694:1: warning: adding 'int' to a string does not append to the string [-Wstring-plus-int]
  694 | CROSS_PLATFORM_UUIDOF(IDxcVersionInfo2, "fb6904c4-42f0-4b62-9c46-983af7da7c83")
      | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/microsoft/compiler/dxcapi.h:114:59: note: expanded from macro 'CROSS_PLATFORM_UUIDOF'
  114 |        byte_from_hexstr(spec + 32), byte_from_hexstr(spec + 34))

Note: spec is a string literal: "fb6904c4-42f0-4b62-9c46-983af7da7c83"

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36707>
 2025-08-13 11:32:27 +00:00
Caleb Callaway
20171f23d6 spirv: Fix RT raygen hit attribute validation error 
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13677
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36729>
 2025-08-13 10:20:35 +00:00
Job Noorman
6d779e900c ir3: allow shared srcs for ldc 
This works just fine and opens up a lot more opportunities for early
preamble. Note that I haven't seen actual cases where the index is large
enough to need a register but verified in computerator that it works.

Totals:
MaxWaves: 2377396 -> 2377428 (+0.00%); split: +0.00%, -0.00%
Instrs: 48194946 -> 48173991 (-0.04%); split: -0.10%, +0.06%
CodeSize: 101878832 -> 101892290 (+0.01%); split: -0.06%, +0.07%
NOPs: 8383282 -> 8362061 (-0.25%); split: -0.46%, +0.20%
MOVs: 1468620 -> 1464570 (-0.28%); split: -1.14%, +0.86%
COVs: 823514 -> 823506 (-0.00%); split: -0.00%, +0.00%
Full: 1716474 -> 1714338 (-0.12%); split: -0.13%, +0.01%
(ss): 1112861 -> 1117802 (+0.44%); split: -0.52%, +0.96%
(sy): 552143 -> 553148 (+0.18%); split: -0.31%, +0.49%
(ss)-stall: 4011510 -> 4018364 (+0.17%); split: -0.26%, +0.43%
(sy)-stall: 16736200 -> 16766871 (+0.18%); split: -0.39%, +0.57%
STPs: 18895 -> 18887 (-0.04%)
LDPs: 23853 -> 23845 (-0.03%)
Preamble Instrs: 11502184 -> 11461058 (-0.36%); split: -0.48%, +0.12%
Early Preamble: 121333 -> 125474 (+3.41%)
Last helper: 11683394 -> 11675574 (-0.07%); split: -0.14%, +0.07%
Subgroup size: 12951168 -> 12952320 (+0.01%)
Cat0: 9238171 -> 9217761 (-0.22%); split: -0.42%, +0.20%
Cat1: 2352968 -> 2348920 (-0.17%); split: -0.71%, +0.54%
Cat2: 17464877 -> 17468941 (+0.02%); split: -0.00%, +0.03%
Cat6: 515664 -> 515648 (-0.00%)
Cat7: 1636736 -> 1636191 (-0.03%); split: -0.33%, +0.29%

Totals from 12861 (7.81% of 164705) affected shaders:
MaxWaves: 141814 -> 141846 (+0.02%); split: +0.07%, -0.05%
Instrs: 12731084 -> 12710129 (-0.16%); split: -0.39%, +0.22%
CodeSize: 24749138 -> 24762596 (+0.05%); split: -0.23%, +0.29%
NOPs: 2744093 -> 2722872 (-0.77%); split: -1.40%, +0.62%
MOVs: 492373 -> 488323 (-0.82%); split: -3.39%, +2.57%
COVs: 170074 -> 170066 (-0.00%); split: -0.01%, +0.00%
Full: 224044 -> 221908 (-0.95%); split: -1.00%, +0.05%
(ss): 325836 -> 330777 (+1.52%); split: -1.76%, +3.28%
(sy): 143661 -> 144666 (+0.70%); split: -1.20%, +1.89%
(ss)-stall: 1397335 -> 1404189 (+0.49%); split: -0.75%, +1.24%
(sy)-stall: 4286193 -> 4316864 (+0.72%); split: -1.52%, +2.24%
STPs: 1628 -> 1620 (-0.49%)
LDPs: 2183 -> 2175 (-0.37%)
Preamble Instrs: 2486870 -> 2445744 (-1.65%); split: -2.23%, +0.57%
Early Preamble: 170 -> 4311 (+2435.88%)
Last helper: 3053311 -> 3045491 (-0.26%); split: -0.52%, +0.26%
Subgroup size: 991296 -> 992448 (+0.12%)
Cat0: 3031604 -> 3011194 (-0.67%); split: -1.29%, +0.61%
Cat1: 667377 -> 663329 (-0.61%); split: -2.50%, +1.90%
Cat2: 4485219 -> 4489283 (+0.09%); split: -0.01%, +0.10%
Cat6: 87365 -> 87349 (-0.02%)
Cat7: 731126 -> 730581 (-0.07%); split: -0.73%, +0.65%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36674>
 2025-08-13 09:59:14 +00:00
Seán de Búrca
c579b8eff6 rusticl: adjust naming and assert usage for clarity 
v2: make naming consistent across functions, incorporate earlier naming
changes

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
 2025-08-13 09:37:45 +00:00
Seán de Búrca
808484041c rusticl: execute program builds as jobs on a worker thread 
v2: rework to use Rust closure for worker job function
v3: split preparatory restructuring into separate commit
v4: parallelize link and compile, adjust thread/job count
v5: split out naming changes to later commit, move validation to api/

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
 2025-08-13 09:37:45 +00:00
Seán de Búrca
56cc1b1c96 rusticl: restructure program build to prepare for parallelization 
v2: include restructuring of link and compile, break out more functions
v3: split out naming changes to later commit

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
 2025-08-13 09:37:45 +00:00
Seán de Búrca
833481b6ab rusticl: introduce intermediate header object 
This lets us take ownership of the header object without worrying about
lifetimes, enabling parallelization.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36497>
 2025-08-13 09:37:44 +00:00