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Rohan Garg e21cca78ea anv,blorp,iris: Set PreferredSLMAllocationSize on gfx125+ 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>
 2023-04-06 10:54:47 +00:00
Rohan Garg 3b6dbf8902 intel/genxml: Add the preferred slm size enum for gen125 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>
 2023-04-06 10:54:46 +00:00
Anuj Phogat 606a39f9d1 intel/genxml/125: Add preferred SLM allocation size field 
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>
 2023-04-06 10:54:46 +00:00
Jesse Natalie 767c5425da CI/windows: Increase timeout for build container job 
These jobs can take upwards of 40 minutes just to upload
the built container images...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22320>
 2023-04-06 09:14:22 +00:00
Jesse Natalie 24fce05f3f CI/windows: Update headers and Agility redist to 1.710.0-preview 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22320>
 2023-04-06 09:14:22 +00:00
Timothy Arceri 5a29af262c glsl: move some GL ES checks to the NIR linker 
Eventually we should aim to remove the GLSL IR linker.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22305>
 2023-04-06 08:07:35 +00:00
Timothy Arceri bf8f11a2de mesa: add _mesa_is_api_gles2() helper 
The glsl compiler has been reworked to avoid passing gl_context around
so that we can avoid expensive recompiles across the code base for
minor changes. This helper will help us avoid passing gl_context around
where its otherwise unrequired.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22305>
 2023-04-06 08:07:35 +00:00
Sergi Blanch Torne 86ad0356b6 ci: disable Collabora's LAVA lab for maintance 
This is to inform you of some planned downtime in the LAVA lab as follows:

    Start: 2023-04-06 07:30 GMT
    End: 2023-04-06 09:00 GMT

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22185>
 2023-04-06 06:04:57 +00:00
Chia-I Wu a38de4c011 radv: disable tc_compatible_cmask on GFX9 in some cases 
There seems to be issues when sample count > 2 on GFX9.  More precisely,
CTS has issues when sample count > 2.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21615>
 2023-04-06 05:27:01 +00:00
Chia-I Wu bd5fb29db6 radv: add RADV_FMASK_COMPRESSION_PARTIAL 
RADV_FMASK_COMPRESSION_PARTIAL means the fmask is decompressed but not
expanded.  It is desired for sampling when the cmask is not
TC-compatible.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21615>
 2023-04-06 05:27:01 +00:00
Chia-I Wu 3cf7ac4e9c radv: rework radv_layout_fmask_compressed 
Rename radv_layout_fmask_compressed and make it return an enum.  We will
add partial compression (fmask decompressed and not expanded) in a
following commit.

Drop the check for VK_IMAGE_USAGE_STORAGE_BIT and
VK_IMAGE_USAGE_TRANSFER_DST_BIT.  When transitioning to
VK_IMAGE_LAYOUT_GENERAL, we should decompress and expand FMASK even when
those usage bits are not set.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21615>
 2023-04-06 05:27:01 +00:00
Emma Anholt 8e84a23697 ci/zink: Disable a630 portal-2-v2 due to kernel OOMs. 
It's been popular for flakes due to oomkilling or kernel kmalloc failure
recently.  Is it ultimately the source of running out of memory?  Who
knows, but hopefully it's at least a big part of the problem.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt ffa867b535 tgsi: Drop TGSI_OPCODE_DFRACEXP. 
This is no longer emitted by nir_to_tgsi, so let's drop it.  This unlocks
some more TGSI DCE, since now all instructions have a single dest, but
that's a project for another day.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt ba5bc2677f glsl: Drop PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED. 
All drivers should now be using the appropriate NIR lowering, so we can
drop this pile of code.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt 7325f699db glsl: Drop frontend lowering of 32-bit frexp. 
All the users should now be calling the appropriate NIR lowering function.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt fca4857091 nir_to_tgsi: Always lower frexp_exp/sig. 
The GLSL frontend was already lowering 32-bit frexp, so only 64-bit frexp
is possible as an op in the incoming NIR.  However, svga and nouveau don't
set PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED, leaving just r600's
non-default TGSI mode potentially using it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt 3f2328c629 panfrost/midgard: Enable nir_lower_frexp. 
Needed for dropping the GLSL frontend lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt 094b5a71d7 agx: Enable nir_lower_frexp. 
Needed for Vulkan, and for dropping GLSL frontend lowering for the deqp
coverage override case.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt 862235ecaa v3d: Lower frexp in the GL compiler like we do in Vulkan. 
Needed for dropping GLSL's frontend lowering.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt 04c31c6ada zink: Enable nir_lower_frexp. 
This will enable GLSL to drop its frexp lowering in the frontend.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt 7c57061b77 nouveau: Enable frexp lowering in the backend. 
This would be desired for NVK using this backend, but also for getting
lowering out of the GLSL frontend.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt 3a336a8ffd nouveau: Add missing nir_opt_algebraic_late. 
This was needed for nir_lower_frexp, but it's a win anyway.  shader-db
results:

total gpr in shared programs: 1143621 -> 1143502 (-0.01%)
gpr in affected programs: 33918 -> 33799 (-0.35%)

total instructions in shared programs: 7829415 -> 7820124 (-0.12%)
instructions in affected programs: 1204967 -> 1195676 (-0.77%)

total bytes in shared programs: 71802760 -> 71717352 (-0.12%)
bytes in affected programs: 11031888 -> 10946480 (-0.77%)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt f2228902ed ir3: Move turnip's nir_lower_frexp to the shared compiler. 
We had NIR lowering for Vulkan, and rely on GLSL's lowering in the
frontend, but this will let us drop the GLSL lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt f1ea6c1b40 intel: Always call nir_lower_frexp. 
We have NIR lowering for Vulkan, and rely on GLSL's lowering in the
frontend, but this will let us drop the GLSL lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt fb60edf4e9 state_tracker: Lower frexp before lowering doubles. 
We don't have softfp64 for frexp, it has been lowered in GLSL up until
now.  I didn't bother splitting out 32 from 64 because it's not worth any
effort.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt 261c1f9ee1 glsl/softfp64: Add fisfinite lowering. 
This is generated by nir_lower_frexp, and if we leave fisfinite in place
then the late algebraic pass lowering it to this pattern will cause an
un-lowered fabs64 to be emitted.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:01 +00:00
Emma Anholt 7ff899dd6e glsl/softfp64: GC the temp vars after we lower them to SSA. 
They don't serve any purpose other than taking up memory and cluttering
your compiler output at this point.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:00 +00:00
Emma Anholt 2a33ea95d6 glsl: Retire ldexp lowering in favor of the nir lowering flag. 
Compilers need to set the nir flag anyway for vulkan, so just pass ldexp
through to NIR and let that handle it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:00 +00:00
Emma Anholt 675f4ff596 zink: Add mapping for nir_op_ldexp, but disable it for 64-bit's sake. 
We previously had GLSL do ldexp lowering to bitops, but NIR can do it
instead.  It's tempting to just pass the NIR op through to the host Vulkan
driver, but to do that we'd need to split up NIR's flag between 32 and
64-bit support, and that's not worth anyone's time for an op we've never
seen used.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:00 +00:00
Emma Anholt 46bf687882 glsl: Move ForceGLSLAbsSqrt handling to glsl-to-nir. 
Cutting more GLSL lowering pass in favor of nir builder.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
 2023-04-06 02:32:00 +00:00
Mike Blumenkrantz a73c28fdce radv: fix leak of nir from retained shaders 
if shaders are found in the app cache above, execution will goto done:
and the nir must still be freed

Fixes: 03d2bd6042 ("radv: ensure to retain NIR shaders for GPL libs found in the cache")

fixes #8786

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22317>
 2023-04-06 01:53:28 +00:00
Eric Engestrom e6c84b8a00 panfrost: assign the correct create_for_resource from the start 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22322>
 2023-04-05 23:15:35 +00:00
Rob Clark 66d4dbd960 util/disk_cache: Move blob_put_cb to the async queue 
Move deflate and put to the queue for the blob cache case.  This moves
the overhead out of the app thread when storing new shaders.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22248>
 2023-04-05 20:25:04 +00:00
Rob Clark dab1bd5a77 util/disk_cache: Use queue state to skip put 
If we move the blob-cache path into the async queue, then
path_init_failed is no longer a good way to check if puts
should be a no-op.  But fortunately checking if the queue
is initialized is, and is a more obvious check because
what it is guarding is a util_queue_add_job().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22248>
 2023-04-05 20:25:04 +00:00
Rob Clark 213627e94b util/disk_cache: Add NONE type 
Add an explicit enum for the DISK_CACHE_NONE type so that we don't
confuse with the MULTI_FILE case on android when the blob-cache is
used.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22248>
 2023-04-05 20:25:04 +00:00
Rob Clark afb350906e util/disk_cache: Split out queue initialization 
Split out a helper to initialize the queue, as we'll want to re-use this
for the blob-cache case.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22248>
 2023-04-05 20:25:04 +00:00
Jordan Justen eef7a117a1 intel/compiler: Support fmul_fsign opt for fp64 when int64 isn't supported 
MTL support fp64, but not int64. The fsign(double(x))*FOO optimization
would try to use a 64-bit int xor operation to conditionally toggle
the sign bit off the result.

Since this only affects high bit of the result, we can do a 32-bit
move of the low dword, and a 32-bit xor on the high dword.

Fixes dEQP-VK.spirv_assembly.instruction.compute.float_controls.fp64.input_args.modf_denorm_flush_to_zero
on MTL.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22259>
 2023-04-05 18:48:21 +00:00
Timur Kristóf 7abd8c499b radv/amdgpu: Remove can_patch and chained submit code path. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>
 2023-04-05 17:10:25 +00:00
Timur Kristóf 6aa518ea86 radv: Chain cmd buffers in queue code when possible, not in winsys. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>
 2023-04-05 17:10:25 +00:00
Timur Kristóf c876e99aa4 radv/amdgpu: Unchain CS array in queue code not in winsys. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>
 2023-04-05 17:10:25 +00:00
Timur Kristóf 44f7e42665 radv/amdgpu: Walk chained CS objects for BO list. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>
 2023-04-05 17:10:25 +00:00
Timur Kristóf d7fc114788 radv/amdgpu: Remember which CS the current one is chained to. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>
 2023-04-05 17:10:25 +00:00
Timur Kristóf ba87ade6d0 radv/amdgpu: Extract radv_amdgpu_add_cs_to_bo_list function. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>
 2023-04-05 17:10:25 +00:00
Timur Kristóf 9d22125f05 radv/amdgpu: Expose CS chain and unchain on the winsys. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>
 2023-04-05 17:10:25 +00:00
Timur Kristóf aa9558698e radv/amdgpu: Extract CS chain and unchain functions. 
Also add a comment that explains what chaining means
and add a check to make sure the HW IP type supports it.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>
 2023-04-05 17:10:25 +00:00
David Heidelberg e261e46c09 ci: implement sections for cuttlefish 
Reviewed-by: Helen Koike <helen.koike@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22005>
 2023-04-05 16:26:20 +00:00
Samuel Pitoiset 981f512037 radv: emit the PS epilog after the graphics pipeline 
Otherwise, SPI_SHADER_PGM_RSRC1_PS is overwritten when the graphics
pipeline is emitted.

Fixes: 5c362cde33 ("radv: update PS num_vgprs in case of epilogs rather than overallocating VGPRs")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22310>
 2023-04-05 14:48:00 +00:00
Eric Engestrom 368a6f2330 vc4/ci: add another sync flake 
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/39377396

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22312>
 2023-04-05 14:15:25 +00:00
Mike Blumenkrantz a17317d2a0 glthread: use id 0 for internal buffer objects 
-1 is an invalid buffer index which breaks app expectations, specifically
apitrace, which checks for return value of 0 from checking buffer bindings
to determine whether to inject user vertex buffer bindings and create functional
traces

this should fix capturing traces with drivers using glthread

fixes #8383

cc: mesa-stable

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22293>
 2023-04-05 13:28:44 +00:00
Lionel Landwerlin e25aee8e34 intel/fs: also allow vec8+ vectorization of load_global_const_block_intel 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>
 2023-04-05 12:32:56 +00:00