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nir_to_tgsi: Always lower frexp_exp/sig.

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The GLSL frontend was already lowering 32-bit frexp, so only 64-bit frexp
is possible as an op in the incoming NIR.  However, svga and nouveau don't
set PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED, leaving just r600's
non-default TGSI mode potentially using it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>
This commit is contained in:
Emma Anholt
2023-03-22 14:13:06 -07:00
committed by Marge Bot
parent 3f2328c629
commit fca4857091
1 changed files with 4 additions and 32 deletions
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src/gallium/auxiliary/nir/nir_to_tgsi.c
+4 -32
View File
@@ -1685,40 +1685,10 @@ ntt_emit_alu(struct ntt_compile *c, nir_alu_instr *instr)
ntt_CMP(c, dst, src[0], src[2], src[1]);
break;
/* It would be nice if we could get this left as scalar in NIR, since
* the TGSI op is scalar.
*/
case nir_op_frexp_sig:
case nir_op_frexp_exp: {
assert(src_64);
struct ureg_dst temp = ntt_temp(c);
for (int chan = 0; chan < 2; chan++) {
int wm = 1 << chan;
if (!(instr->dest.write_mask & wm))
continue;
struct ureg_dst dsts[2] = { temp, temp };
if (instr->op == nir_op_frexp_sig) {
dsts[0] = ureg_writemask(dst, ntt_64bit_write_mask(wm));
} else {
dsts[1] = ureg_writemask(dst, wm);
}
struct ureg_src chan_src = ureg_swizzle(src[0],
chan * 2, chan * 2 + 1,
chan * 2, chan * 2 + 1);
struct ntt_insn *insn = ntt_insn(c, TGSI_OPCODE_DFRACEXP,
dsts[0], chan_src,
ureg_src_undef(),
ureg_src_undef(),
ureg_src_undef());
insn->dst[1] = dsts[1];
}
case nir_op_frexp_exp:
unreachable("covered by nir_lower_frexp()");
break;
}
case nir_op_ldexp:
assert(dst_64); /* 32bit handled in table. */
@@ -3934,6 +3904,8 @@ const void *nir_to_tgsi_options(struct nir_shader *s,
/* Lower demote_if to if (cond) { demote } because TGSI doesn't have a DEMOTE_IF. */
NIR_PASS_V(s, nir_lower_discard_if, nir_lower_demote_if_to_cf);
NIR_PASS_V(s, nir_lower_frexp);
bool progress;
do {
progress = false;