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Author SHA1 Message Date
Dawn Han d5f116feb5 Update bitset when init descriptor layout. 
Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17505>
 2022-09-02 21:15:43 +00:00
Dawn Han 7039467522 Increase enum type in vn_descriptor_set. 
Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17505>
 2022-09-02 21:15:43 +00:00
David Heidelberg 250c684750 ci: uprev piglit 2022-08-30 
Acked-by: Juan A. Suarez <jasuarez@igalia.com>  # for broadcom
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>  # for zink
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18318>
 2022-09-02 20:15:28 +00:00
Chia-I Wu c93173fcec util/perf: use ALWAYS_INLINE for tracepoints 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18309>
 2022-09-02 19:46:50 +00:00
Chia-I Wu 4d747d5690 util/perf: simplify u_trace_instrument 
When ut_perfetto_enabled changes, update _u_trace_instrument as well.
This allows u_trace_instrument to check just a single variable.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18309>
 2022-09-02 19:46:50 +00:00
Chia-I Wu 18d7cb4abb util/perf: add u_trace_instrument 
It is called from tracepoints.  When it returns false, instrumentation
is disabled.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18309>
 2022-09-02 19:46:50 +00:00
Chia-I Wu aeb2c5a8da util/perf: remove u_trace::enabled 
We can set ut_trace_instrument when either GPU_TRACE or
GPU_TRACE_INSTRUMENT is set.  This results in one less variable to check
in tracepoints.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18309>
 2022-09-02 19:46:50 +00:00
Chia-I Wu 8d8d4347e3 util/perf: ignore ut->enabled for iterators 
With perfetto, instrumentation can be enabled in the middle of cmd
buffer recording even when ut->enabled is false.  It might be better to
be consistent and ignore ut->enabled for iterators.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18309>
 2022-09-02 19:46:50 +00:00
Mike Blumenkrantz 8b15025a2b mesa: add GLSL_SOURCE 
many times I just want to dump glsl and not a trillion lines of IR

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18280>
 2022-09-02 19:15:44 +00:00
Marcin Ślusarz 9701b9098f anv: enable EXT_mesh_shader 
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
 2022-09-02 17:40:47 +00:00
Marcin Ślusarz d5dedecfe7 anv: implement draw calls for EXT_mesh_shader 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
 2022-09-02 17:40:47 +00:00
Marcin Ślusarz 637063ffc6 anv: implement EXT_mesh_shader 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
 2022-09-02 17:40:47 +00:00
Marcin Ślusarz b3354afd89 anv: replace VK_SHADER_STAGE_[TASK|MESH]_BIT_NV with VK_SHADER_STAGE_[TASK|MESH]_BIT_EXT 
They have the same numerical values, so nothing changes.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
 2022-09-02 17:40:47 +00:00
Marcin Ślusarz 9cefaa9b6d anv: check EXT_mesh_shader whenever NV_mesh_shader is checked 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
 2022-09-02 17:40:47 +00:00
Marcin Ślusarz 2e1b96bb1b intel/compiler: implement EXT_mesh_shader 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
 2022-09-02 17:40:47 +00:00
Emma Anholt 3ef13ef234 turnip: Treating non-d/s-write pipelines as not having d/s feedback loops. 
A subpass in gfxbench has the depth buffer present, but not written to,
for a render pass using the depth buffer as an input attachment.  We can
skip single-prim-mode and the associated "oh no don't use sysmem" in that
case.

Improves gfxbench vk-5-normal perf by 1.56193% +/- 0.0743035% (n=14).
Part of #6327.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18241>
 2022-09-02 16:47:02 +00:00
Marcin Ślusarz 14911e8f83 spirv, compiler: add "bool nv" to shader_info.mesh 
Not knowing whether we deal with the NV or EXT extension
makes implementation difficult for Intel HW.
NV support will be dropped at some point, so
this ugliness will go away eventually.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
 2022-09-02 16:18:33 +00:00
Timur Kristóf 7d1bcf1f55 spirv, nir: Handle EmitMeshTasksEXT opcode. 
A task shader must use this instruction to specify the dimensions
of the launched mesh shader workgroups.
It is a terminating instruction.

When the task shader doesn't have the optional payload, use the
pre-existing launch_mesh_workgroups intrinsics.

When the task shader has a payload, use a new
launch_mesh_workgroups_with_payload_deref intrinsics which has
a deref that refers to the payload variable.

We also add this new intrinsic to nir_lower_io which lowers this
to the pre-existing explicit intrinsic.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
 2022-09-02 16:18:33 +00:00
Timur Kristóf 42e906485c spirv: Support TaskPayloadWorkgroupEXT storage class. 
Just use the task_payload NIR storage class for this.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
 2022-09-02 16:18:33 +00:00
Timur Kristóf a03c30bd8d spirv: Support the CullPrimitiveEXT mesh shader built-in. 
This is a per-primitive builtin output which indicates that a
primitive should be culled (deleted) from the output.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
 2022-09-02 16:18:33 +00:00
Timur Kristóf c5c6cef893 spirv: Support EXT_mesh_shader SetMeshOutputsEXT. 
Use the set_vertex_and_primitive_count intrinsic to
express the number of vertices and primitives that the
mesh shader workgroup outputs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
 2022-09-02 16:18:33 +00:00
Timur Kristóf b3cc09cff3 spirv: Support EXT_mesh_shader mesh/task stages. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
 2022-09-02 16:18:33 +00:00
Timur Kristóf bbebc1fb35 spirv: Add mesh_shading capability for EXT_mesh_shader. 
Indicates support for the EXT_mesh_shader SPIR-V capabilities.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
 2022-09-02 16:18:33 +00:00
Timur Kristóf f6925b8446 spirv: Support EXT_mesh_shader indices and mark them per-primitive. 
They are not defined as per-primitive in the EXT, but they behave
like per-primitive outputs so it's easier to treat them like that.
They may still require special treatment in the backend in order to
control where and how they are stored.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
 2022-09-02 16:18:33 +00:00
Timur Kristóf c315e2e718 vulkan, spirv: Update to Vulkan 1.3.226 and latest SPIR-V headers. 
Done using the "khronos-update.py" script, leaving out parts that
are not relevant to Vulkan.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
 2022-09-02 16:18:33 +00:00
Alyssa Rosenzweig 3bf3c45ae8 pan/bi: Add and use bi_num_successors helper 
Makes a few patterns easier to read.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:24 +00:00
Alyssa Rosenzweig 875a34160a pan/bi: Add and use bi_replace_src helper 
This is a common pattern. Make it more ergonomic. With the help of Coccinelle:

   @@
   expression E;
   expression R;
   expression instruction;
   @@

   -instruction->src[E] = bi_replace_index(instruction->src[E], R);
   +bi_replace_src(instruction, E, R);

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:24 +00:00
Alyssa Rosenzweig f01ccdbf69 pan/bi: Remove assert(bi_is_ssa(dest)) 
Prior to register allocation, destinations must be in SSA form, except for the
"fake SSA" briefly used in the current RA (for which bi_is_ssa returns true
anyway). These asserts duplicate the asserts in the validator. If there's any
coverage lost here, that's just a sign the validator needs to run more often.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:24 +00:00
Alyssa Rosenzweig 3fbd1e97d3 pan/bi: Strengenth assert in the validator 
We should only see SSA now.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:24 +00:00
Alyssa Rosenzweig 98c69de80d pan/bi: Add and use bi_foreach_ssa_src macro 
Frequently, we want to iterate over the SSA variables read by an instruction,
while skipping over constants and uniforms. Add and use a macro for this
pattern. A few redundant asserts are removed.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:24 +00:00
Alyssa Rosenzweig d3acfd9be8 pan/bi: Simplify bi_get_index prototype 
2/3 of its arguments are now unused.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:24 +00:00
Alyssa Rosenzweig 93cf569b4a pan/bi: Remove bi_max_temp 
This is no longer needed given the flat indexing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:24 +00:00
Alyssa Rosenzweig a4eebb556a pan/bi: Inline node_to_index 
One user, now trivial.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:24 +00:00
Alyssa Rosenzweig 46e6e99f09 pan/bi: Get rid of bi_get_node 
Now that variables have flat naming (no more SSA/reg distinction), we can just
use .value directly. This cleans up the RA a bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:24 +00:00
Alyssa Rosenzweig 1699d98e8e pan/bi: Remove NIR registers from the IR 
They are now unused, so normal == SSA at this point.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:24 +00:00
Alyssa Rosenzweig f6abcf534a pan/bi: Move non-SSA liveness into RA 
Now that non-SSA nodes are an internal implementation detail of RA, the
entrypoints should be made private to make sure no other passes use the
RA-specific liveness analysis.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig 30528bac5a pan/bi: Assume SSA for helper invocation analysis 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig 94511618be pan/bi: Assume SSA when translating NIR 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig fad0837ee3 pan/bi: Assume SSA when scheduling for pressure 
This is much simpler now: entire hazards become impossible when the program is
kept in SSA form.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig f02f657a31 pan/bi: Assume SSA in minor passes 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig 334ab03b9f pan/bi: Assume non-null sources in constant folding 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig efee0ddd91 pan/bi: Assume SSA in CSE 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig 0e456da750 pan/bi: Assume SSA in mod prop 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig e94e6c49f1 pan/bi: Assume SSA in copyprop 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig 8244965868 pan/bi: Don't use bi_temp_reg 
We've already broken SSA irreparably at this point. We can just change what
"normal" means and avoid the disjointed indexing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig cefec430a3 pan/bi: Clear reg in squeeze_index 
SSA is broken at this point. Let's not pretend otherwise. The numbering produced
by squeeze_index already disambiguates what-used-to-be SSA variables and
registers. A few shader-db changes because this shuffles the register allocation
around because LCRA is stupid.

total instructions in shared programs: 2658849 -> 2650196 (-0.33%)
instructions in affected programs: 463733 -> 455080 (-1.87%)
helped: 1089
HURT: 135
helped stats (abs) min: 1.0 max: 43.0 x̄: 8.20 x̃: 5
helped stats (rel) min: 0.11% max: 17.05% x̄: 2.28% x̃: 1.52%
HURT stats (abs)   min: 1.0 max: 7.0 x̄: 2.07 x̃: 2
HURT stats (rel)   min: 0.10% max: 2.97% x̄: 1.03% x̃: 0.83%
95% mean confidence interval for instructions value: -7.52 -6.62
95% mean confidence interval for instructions %-change: -2.04% -1.78%
Instructions are helped.

total cycles in shared programs: 140617.52 -> 140613.14 (<.01%)
cycles in affected programs: 227.45 -> 223.08 (-1.92%)
helped: 45
HURT: 1
helped stats (abs) min: 0.015625 max: 0.4375 x̄: 0.10 x̃: 0
helped stats (rel) min: 0.43% max: 17.72% x̄: 2.79% x̃: 1.29%
HURT stats (abs)   min: 0.015625 max: 0.015625 x̄: 0.02 x̃: 0
HURT stats (rel)   min: 1.47% max: 1.47% x̄: 1.47% x̃: 1.47%
95% mean confidence interval for cycles value: -0.12 -0.07
95% mean confidence interval for cycles %-change: -3.76% -1.64%
Cycles are helped.

total cvt in shared programs: 13877.61 -> 13742.41 (-0.97%)
cvt in affected programs: 3432 -> 3296.80 (-3.94%)
helped: 1089
HURT: 135
helped stats (abs) min: 0.015625 max: 0.671875 x̄: 0.13 x̃: 0
helped stats (rel) min: 0.18% max: 28.36% x̄: 5.05% x̃: 3.38%
HURT stats (abs)   min: 0.015625 max: 0.109375 x̄: 0.03 x̃: 0
HURT stats (rel)   min: 0.15% max: 8.33% x̄: 2.87% x̃: 2.27%
95% mean confidence interval for cvt value: -0.12 -0.10
95% mean confidence interval for cvt %-change: -4.46% -3.88%
Cvt are helped.

total quadwords in shared programs: 1442328 -> 1437776 (-0.32%)
quadwords in affected programs: 106240 -> 101688 (-4.28%)
helped: 478
HURT: 17
helped stats (abs) min: 8.0 max: 24.0 x̄: 9.81 x̃: 8
helped stats (rel) min: 1.54% max: 20.00% x̄: 5.27% x̃: 3.70%
HURT stats (abs)   min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
HURT stats (rel)   min: 1.61% max: 14.29% x̄: 6.42% x̃: 6.25%
95% mean confidence interval for quadwords value: -9.61 -8.78
95% mean confidence interval for quadwords %-change: -5.20% -4.54%
Quadwords are helped.

total threads in shared programs: 53557 -> 53550 (-0.01%)
threads in affected programs: 14 -> 7 (-50.00%)
helped: 0
HURT: 7
HURT stats (abs)   min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -1.00 -1.00
95% mean confidence interval for threads %-change: -50.00% -50.00%
Threads are HURT.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig 7a5c8b920a pan/bi: Clean up after converting to SSA 
nir_invalidate_divergence was introduced in aa765c54bd ("pan/bi: Add divergent
intrinsic lowering pass"), which needed divergence information for a late NIR
pass but not otherwise in the backend. Unfortunately, nir_convert_from_ssa is
less aggressive about coalescing when divergence information makes it look like
the coalescing would make the code worse -- even though that's not actually an
issue on Mali.

Now that we don't use nir_convert_from_ssa, we don't need the hack.

Likewise for the vec.reg hack, which was introduced because the split/collect
cache relies on SSA form.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig 28a9486f3a pan/bi: Preserve SSA form from NIR 
Don't call nir_convert_from_ssa, preserve the SSA from NIR. This gets us real
SSA for all frontend passes. The RA becomes a black box that takes SSA in and
outputs register allocated code out. The "broken" SSA form never escapes RA,
which means we can clean up special cases in the rest of the compiler. It also
gets us ready for exploiting SSA form in the RA itself.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig 8fb415fee2 pan/bi: Reduce some moves when going out-of-SSA 
This is still pretty brainless.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00
Alyssa Rosenzweig 9c18873017 pan/bi: Add brainless out-of-SSA pass 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
 2022-09-02 16:03:23 +00:00