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pan/bi: Remove assert(bi_is_ssa(dest))

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Prior to register allocation, destinations must be in SSA form, except for the
"fake SSA" briefly used in the current RA (for which bi_is_ssa returns true
anyway). These asserts duplicate the asserts in the validator. If there's any
coverage lost here, that's just a sign the validator needs to run more often.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
This commit is contained in:
Alyssa Rosenzweig
2022-07-26 12:27:27 -04:00
committed by Marge Bot
parent 3fbd1e97d3
commit f01ccdbf69
2 changed files with 5 additions and 15 deletions
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src/panfrost/bifrost/bi_opt_mod_props.c
-1
View File
@@ -417,7 +417,6 @@ bi_opt_mod_prop_backward(bi_context *ctx)
/* Need to see through the split in a
* ld_var_imm/split/var_tex sequence
*/
assert(bi_is_ssa(use->dest[0]));
bi_instr *tex = uses[use->dest[0].value];
if (!tex || BITSET_TEST(multiple, use->dest[0].value))
src/panfrost/bifrost/bi_ra.c
+5 -14
View File
@@ -215,8 +215,7 @@ bi_liveness_ins_update_ra(uint8_t *live, bi_instr *ins)
/* live_in[s] = GEN[s] + (live_out[s] - KILL[s]) */
bi_foreach_dest(ins, d) {
if (bi_is_ssa(ins->dest[d]))
live[ins->dest[d].value] &= ~bi_writemask(ins, d);
live[ins->dest[d].value] &= ~bi_writemask(ins, d);
}
bi_foreach_ssa_src(ins, src) {
@@ -345,7 +344,6 @@ bi_mark_interference(bi_block *block, struct lcra_state *l, uint8_t *live, uint6
* interfering with the destination */
bi_foreach_dest(ins, d) {
assert(bi_is_ssa(ins->dest[d]));
unsigned node = ins->dest[d].value;
/* Don't allocate to anything that's read later as a
@@ -455,11 +453,8 @@ bi_allocate_registers(bi_context *ctx, bool *success, bool full_regs)
default_affinity &= BITFIELD64_MASK(48) << 8;
bi_foreach_instr_global(ctx, ins) {
bi_foreach_dest(ins, d) {
assert(bi_is_ssa(ins->dest[d]));
bi_foreach_dest(ins, d)
l->affinity[ins->dest[d].value] = default_affinity;
}
/* Blend shaders expect the src colour to be in r0-r3 */
if (ins->op == BI_OPCODE_BLEND &&
@@ -788,7 +783,7 @@ bi_lower_vector(bi_context *ctx, unsigned first_reg)
src.offset = i;
bi_mov_i32_to(&b, I->dest[i], src);
if (bi_is_ssa(I->dest[i]) && I->dest[i].value < first_reg)
if (I->dest[i].value < first_reg)
remap[I->dest[i].value] = src;
}
@@ -796,7 +791,7 @@ bi_lower_vector(bi_context *ctx, unsigned first_reg)
} else if (I->op == BI_OPCODE_COLLECT_I32) {
bi_index dest = I->dest[0];
assert(dest.offset == 0);
assert(((bi_is_ssa(dest) && dest.value < first_reg) || I->nr_srcs == 1) && "nir_lower_phis_to_scalar");
assert(((dest.value < first_reg) || I->nr_srcs == 1) && "nir_lower_phis_to_scalar");
bi_foreach_src(I, i) {
if (bi_is_null(I->src[i]))
@@ -834,9 +829,7 @@ bi_lower_vector(bi_context *ctx, unsigned first_reg)
bool all_null = true;
bi_foreach_dest(ins, d) {
if (!bi_is_ssa(ins->dest[d]))
all_null = false;
else if (live[ins->dest[d].value] & bi_writemask(ins, d))
if (live[ins->dest[d].value] & bi_writemask(ins, d))
all_null = false;
}
@@ -945,8 +938,6 @@ bi_out_of_ssa(bi_context *ctx)
if (I->op != BI_OPCODE_PHI)
break;
assert(bi_is_ssa(I->dest[0]));
/* Assign a register for the phi */
bi_index reg = bi_temp(ctx);
assert(reg.value >= first_reg);