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pan/bi: Clean up after converting to SSA

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nir_invalidate_divergence was introduced in aa765c54bd ("pan/bi: Add divergent
intrinsic lowering pass"), which needed divergence information for a late NIR
pass but not otherwise in the backend. Unfortunately, nir_convert_from_ssa is
less aggressive about coalescing when divergence information makes it look like
the coalescing would make the code worse -- even though that's not actually an
issue on Mali.

Now that we don't use nir_convert_from_ssa, we don't need the hack.

Likewise for the vec.reg hack, which was introduced because the split/collect
cache relies on SSA form.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
This commit is contained in:
Alyssa Rosenzweig
2022-05-16 19:51:03 -04:00
committed by Marge Bot
parent 28a9486f3a
commit 7a5c8b920a
1 changed files with 0 additions and 30 deletions
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src/panfrost/bifrost/bifrost_compile.c
-30
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@@ -154,15 +154,6 @@ bi_index_to_key(bi_index idx)
static bi_index
bi_extract(bi_builder *b, bi_index vec, unsigned channel)
{
/* Extract caching relies on SSA form. It is incorrect for nir_register.
* Bypass the cache and emit an explicit split for registers.
*/
if (vec.reg) {
bi_instr *I = bi_split_i32_to(b, channel + 1, vec);
I->dest[channel] = bi_temp(b->shader);
return I->dest[channel];
}
bi_index *components =
_mesa_hash_table_u64_search(b->shader->allocated_vec,
bi_index_to_key(vec));
@@ -4465,25 +4456,6 @@ bi_scalarize_filter(const nir_instr *instr, const void *data)
}
}
/* XXX: This is a kludge to workaround NIR's lack of divergence metadata. If we
* keep divergence info around after we consume it for indirect lowering,
* nir_convert_from_ssa will regress code quality since it will avoid
* coalescing divergent with non-divergent nodes. */
static bool
nir_invalidate_divergence_ssa(nir_ssa_def *ssa, UNUSED void *data)
{
ssa->divergent = false;
return true;
}
static bool
nir_invalidate_divergence(struct nir_builder *b, nir_instr *instr,
UNUSED void *data)
{
return nir_foreach_ssa_def(instr, nir_invalidate_divergence_ssa, NULL);
}
/* Ensure we write exactly 4 components */
static nir_ssa_def *
bifrost_nir_valid_channel(nir_builder *b, nir_ssa_def *in,
@@ -4687,8 +4659,6 @@ bi_optimize_nir(nir_shader *nir, unsigned gpu_id, bool is_blend)
NIR_PASS_V(nir, nir_divergence_analysis);
NIR_PASS_V(nir, bi_lower_divergent_indirects,
pan_subgroup_size(gpu_id >> 12));
NIR_PASS_V(nir, nir_shader_instructions_pass,
nir_invalidate_divergence, nir_metadata_all, NULL);
}
}