intel/compiler: implement EXT_mesh_shader
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
This commit is contained in:
committed by
Marge Bot
parent
3ef13ef234
commit
2e1b96bb1b
@@ -7635,7 +7635,9 @@ fs_visitor::emit_work_group_id_setup()
|
||||
bld.MOV(offset(id, bld, 1), r0_6);
|
||||
bld.MOV(offset(id, bld, 2), r0_7);
|
||||
} else {
|
||||
/* Task/Mesh have a single Workgroup ID dimension in the HW. */
|
||||
/* NV Task/Mesh have a single Workgroup ID dimension in the HW. */
|
||||
assert(gl_shader_stage_is_mesh(stage));
|
||||
assert(nir->info.mesh.nv);
|
||||
bld.MOV(offset(id, bld, 1), brw_imm_ud(0));
|
||||
bld.MOV(offset(id, bld, 2), brw_imm_ud(0));
|
||||
}
|
||||
|
||||
@@ -1235,6 +1235,19 @@ fs_visitor::nir_emit_task_mesh_intrinsic(const fs_builder &bld,
|
||||
}
|
||||
break;
|
||||
|
||||
case nir_intrinsic_load_num_workgroups:
|
||||
assert(!nir->info.mesh.nv);
|
||||
dest = retype(dest, BRW_REGISTER_TYPE_UD);
|
||||
bld.SHR(offset(dest, bld, 0), retype(brw_vec1_grf(0, 6), dest.type), brw_imm_ud(16));
|
||||
bld.AND(offset(dest, bld, 1), retype(brw_vec1_grf(0, 4), dest.type), brw_imm_ud(0xffff));
|
||||
bld.SHR(offset(dest, bld, 2), retype(brw_vec1_grf(0, 4), dest.type), brw_imm_ud(16));
|
||||
break;
|
||||
|
||||
case nir_intrinsic_load_workgroup_index:
|
||||
dest = retype(dest, BRW_REGISTER_TYPE_UD);
|
||||
bld.MOV(dest, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD));
|
||||
break;
|
||||
|
||||
default:
|
||||
nir_emit_cs_intrinsic(bld, instr);
|
||||
break;
|
||||
|
||||
Reference in New Issue
Block a user