The tests assumed that isl would be in the include path but that usually
isn't the case. Instead, we usually have src/intel and you need to add an
"isl/" prefix.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
If the surface has a layout of GEN4_2D then we need to compute a normal 2D
alignment and not use the magic linewar 1D alignment.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
The Sky Lake 1D layout is only used if the surface is linear. For tiled
surfaces such as depth and stencil the old gen4 2D layout is used.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
In ca2a8e5628, we updated the format table to add more formats (most of
which are new on SKL) but accidentally marked some integer formats as
filterable. You can't filter an integer format.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
There were a lot of formats where support was added on Haswell or later but
we never updated the format table.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Otherwise, the clear color will get ignored. This prevents assertion
errors if clear color is set to something invalid and aux is not used.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
In all three cases, we start with width and height taken from
isl_surf::phys_slice0_extent_sa which is already in samples. There is no
need to do the conversion and doing so gives us an incorrect value.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
The function takes a logical array layer but was assuming it was a physical
array layer. While we'er here, we also make it not assert-fail on gen9 3-D
surfaces.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
The alignment we use doesn't matter (see the comment) but it should at
least be an alignment we can represent with the enums.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
It's been in elements for a while but, for whatever reason, the parameter
names in the header file never got updated.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This reverts commit 091f1da902 .
Although a user may specify a specfic tiling bit, ISL should still
prevent incompatible tiling/surface combinations.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
When we initially dropped bpb in favor of bs, we accidentally didn't change
this one line properly. This brings it back to what it should be.
Reviewed-by: Chad Versace <chad.versace@intel.com>
A while ago we got rid of the bits-per-block because we thought we didn't
need it. We're about to introduce some very useful 1 and 2-bit formats so
we really should be able to handle them again.
Reviewed-by: Chad Versace <chad.versace@intel.com>
This is based on a very long set of discussions between Chad and myself
about how we should properly represent HiZ and CCS buffers. The end result
of that discussion was that a tiling actually has two different sizes, a
logical size in elements, and a physical size in bytes and rows. This
commit reworks ISL's pitch and size calculations to work in terms of these
two sizes.
Reviewed-by: Chad Versace <chad.versace@intel.com>
We helpfully inserted a PRM quotation about how we need to use
ARRAY_PITCH_SPAN_FULL and then set it to COMPACT. Oops...
Reviewed-by: Chad Versace <chad.versace@intel.com>
The row pitch already specifies the size of a row of elements.
Multiplying by the block height simply causes us to allocate as muc as 12
times more memory than needed for compressed textures.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Commit 87d062a940 ("i965: Fix shared local memory size for Gen9+.")
added u_math.h include which broke the Android build:
In file included from external/mesa3d/src/intel/isl/isl_storage_image.c:25:
In file included from external/mesa3d/src/mesa/drivers/dri/i965/brw_compiler.h:29:
external/mesa3d/src/mesa/main/macros.h:35:10: fatal error: 'util/u_math.h' file not found
^
Add the missing include paths for libmesa_isl.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Kenneth Garunke <kenneth@whitecape.org>
ISL was being a bit too clever for its own good and lowering the format for
us. This is all well and good *if* we always want to lower it. However,
the GL driver selectively lowers the format depending on whether the
surface is write-only or not.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
This field is ignored by the hardware in this case and, on very large 1-D
textures, it can end up being larger than the maximum allowed value.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand