b9ccb00e2c
iris: Enable ctx->Const.UseSTD430AsDefaultPacking
...
hooray for obscurely named pipe caps with bizarre descriptions!
2019-02-21 10:26:10 -08:00
39cb10613c
iris: update comment
2019-02-21 10:26:10 -08:00
f9612e7682
iris: RT flush for memorybarrier with texture bit
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PIXEL_BUFFER_BARRIER_BIT turns into PIPE_BARRIER_TEXTURE and it ought
to trigger an RT flush, according to brw_memory_barrier
2019-02-21 10:26:10 -08:00
2c23721397
iris: PIPE_CONTROL workarounds for GPGPU mode
2019-02-21 10:26:10 -08:00
f1a7392be1
iris: Put batches in an array
...
We keep re-making this array all over the place
2019-02-21 10:26:10 -08:00
c2a77efa71
iris: put render batch first in fence code
...
this shouldn't matter, but it will make the next refactor easier
2019-02-21 10:26:10 -08:00
d918c09975
iris: flush the compute batch too if border pool is redone
2019-02-21 10:26:10 -08:00
017b556609
iris: leave a TODO
2019-02-21 10:26:10 -08:00
f459c56be6
iris: Add fence support using drm_syncobj
2019-02-21 10:26:10 -08:00
db199d9d07
iris: Add wait fences to properly sync between render/compute
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When flushing a batch due to a data dependency, we need to not only
kick off the other batch's work, but stall our execution until it
completes. Just wait on last_syncpt after flushing it.
2019-02-21 10:26:10 -08:00
d69bc4ac12
iris: Hang on to the last batch's sync-point, so we can wait on it
2019-02-21 10:26:10 -08:00
fae74234d9
iris: Tag each submitted batch with a syncobj
...
(adjusted by Ken to make the signalling sync object immediately on
batch reset, rather than batch finish time. this will work better
with deferred flushes...)
2019-02-21 10:26:10 -08:00
3e332af611
iris: Drop vestiges of throttling code
2019-02-21 10:26:10 -08:00
54347c078e
iris: Merge two walks of the exec_bos list
2019-02-21 10:26:10 -08:00
3455f57575
iris: replace vestiges of fence fds with newer exec_fence API
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patch by me and Chris Wilson
2019-02-21 10:26:10 -08:00
11da219be9
iris: Avoid synchronizing due to the workaround BO
2019-02-21 10:26:10 -08:00
30d7bebc8a
iris: Avoid cross-batch synchronization on read/reads
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This avoids flushing batches just because e.g. both are reading the same
dynamic state streaming buffer, or shader assembly buffer.
2019-02-21 10:26:10 -08:00
b21e916a62
iris: Combine iris_use_pinned_bo and add_exec_bo
2019-02-21 10:26:10 -08:00
fb4c898842
iris: Use iris_use_pinned_bo rather than add_exec_bo directly
...
less special this way
2019-02-21 10:26:10 -08:00
e5528151a7
iris: Fix assigning the output handle for exporting for KMS
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Fixes gbm_bo_get_handle() used for KMS in glamor.
2019-02-21 10:26:10 -08:00
01e729f883
iris: Tidy exporting the flink handle
2019-02-21 10:26:10 -08:00
1b69b14c2a
iris: Fix SLM
...
Now that Jason has set up the L3 we can do this. Also, my assert was
useless because we hadn't set up the field in the first place. Oops.
2019-02-21 10:26:10 -08:00
f9c5e277ac
iris: Don't set constant read lengths at upload time
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They're set in derived_data as part of store_cs_state
2019-02-21 10:26:10 -08:00
a90a0e22cb
iris: Configure the L3$ on the compute context
2019-02-21 10:26:10 -08:00
25a41b1aef
iris: properly pin stencil buffers
2019-02-21 10:26:10 -08:00
8545e39808
iris: Fix TCS/TES slot unification
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TCS outputs, TES inputs...not TCS inputs
Fixes some barrier tests
2019-02-21 10:26:10 -08:00
da5590496e
iris: more todo notes
2019-02-21 10:26:10 -08:00
9878ea842f
iris: scissored and mirrored blits
2019-02-21 10:26:10 -08:00
25f194d5ac
iris: more TODO
2019-02-21 10:26:10 -08:00
5207a5f5d5
iris: Fix independent alpha blending.
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independent_blend_enable means per-RT blending, not RGB != A
2019-02-21 10:26:10 -08:00
c06f6d12a5
iris: "Fix" transfer maps of buffers
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x should be in bytes, not cpp units
This generally worked out because PIPE_BUFFER is supposedly required
to be R8_UINT or R8_UNORM. I hear some state trackers pass
PIPE_FORMAT_NONE instead, however, which would make this break.
Just do the right thing directly, to be defensive and clear.
2019-02-21 10:26:10 -08:00
b2c04aa3a0
iris: Fix SourceAlphaBlendFactor
2019-02-21 10:26:10 -08:00
89833eddab
iris: leave another TODO
2019-02-21 10:26:10 -08:00
983e2ae7d2
iris: only clip lower if there's something to clip against
2019-02-21 10:26:10 -08:00
e11c497fc6
iris: fix sysval only binding tables
2019-02-21 10:26:10 -08:00
2ddbc1025e
iris: don't forget to upload CS consts
2019-02-21 10:26:10 -08:00
f1f84a1ae7
iris: drop param stuffs
2019-02-21 10:26:10 -08:00
1b5d35319e
iris: don't trip on param asserts
...
I'd rather not rewrite i965's compute system value handling right now :(
2019-02-21 10:26:10 -08:00
f4829a2fe1
iris: don't support pull constants.
...
I don't think it matters, we won't have any params anyway, but let's
be sure it doesn't try
2019-02-21 10:26:10 -08:00
911f9e8f3f
iris: regather info so we get CLIP_DIST slots, not CLIP_VERTEX
2019-02-21 10:26:09 -08:00
6d19fe376d
iris: enable push constants if we have sysvals but no uniforms
2019-02-21 10:26:09 -08:00
1ef68d77c0
iris: drop iris_setup_push_uniform_range
...
it doesn't do anything, we have no params. I guess I thought there
would be some, but they all get dead code eliminated even if we try
to make them exist in the first place.
2019-02-21 10:26:09 -08:00
7eeb124c02
iris: fix more uniform setup
2019-02-21 10:26:09 -08:00
50743eb748
iris: fix num clip plane consts
2019-02-21 10:26:09 -08:00
a98634a28f
iris: actually upload clip planes.
2019-02-21 10:26:09 -08:00
c60ce3f4fd
iris: bypass params and do it ourselves
...
the backend keeps dead code eliminating them all, so we can't do that,
plus we don't want to because params[] is lame
2019-02-21 10:26:09 -08:00
78fc760bab
iris: dodge backend UCP lowering
2019-02-21 10:26:09 -08:00
deb6d588a6
iris: fix system value remapping
2019-02-21 10:26:09 -08:00
2b0a2915dc
iris: hook up key stuff for clip plane lowering
2019-02-21 10:26:09 -08:00
2876dd1a37
iris: lower user clip planes
2019-02-21 10:26:09 -08:00
Kenneth Graunke