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Jose Fonseca b025c23cfe softpipe: Use STATIC_ASSERT whenever possible. 
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2016-04-12 16:56:15 +01:00
Jose Fonseca 2f13d7543f svga: Use STATIC_ASSERT whenever possible. 
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2016-04-12 16:56:15 +01:00
Jose Fonseca 7279098dc5 mesa: Use STATIC_ASSERT whenever possible. 
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2016-04-12 16:56:15 +01:00
Marek Olšák 686b018ab3 r600g: use common scissor and viewport code 
It's the same as radeonsi. This adds guard band support to r600g.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 17:13:25 +02:00
Marek Olšák 87a5b07f90 gallium/radeon: add R600/Evergreen/Cayman support to common viewport code 
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 17:13:25 +02:00
Marek Olšák 2ca5566ed7 radeonsi: move scissor and viewport states into gallium/radeon 
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 17:13:24 +02:00
Marek Olšák db00f6cc9c radeonsi: use guard band clipping 
Guard band clipping speeds up rasterization for primitives that are
partially off-screen.  This change in particular results in small
framerate improvements in a wide range of games.

Started by Grigori Goronzy <greg@chown.ath.cx>.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 17:12:14 +02:00
Marek Olšák cb21f8a97c radeonsi: compute scissor from viewport in set_viewport_states 
and clamp it right before emitting. This is a prerequisite for computing
the guard band.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:49 +02:00
Marek Olšák 5b6a0b7fc0 gallium/radeon: set GTT WC on tiled textures 
Just for consistency. This should have no effect, because OpenGL textures
always go to VRAM.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák 5a4b74d1ba gallium/radeon: relax requirements on VRAM placements on APUs 
This makes Tonga with vramlimit=128 2x faster in Heaven.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák a57309f807 winsys/amdgpu: remove hack for low VRAM configuration 
A better solution will be used.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák b36f19bf98 r600g: disable aniso filtering for non-mipmap textures on EG 
this is the default behavior of the closed driver when running on VI

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák 3bc2d967c4 r600g: clean up aniso state translation 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák b0d4469519 radeonsi: disable aniso filtering for non-mipmap textures on SI-CI 
The closed driver does this, but it looks at base_level and last_level
and uses a conditional assignment, which LLVM can't generate on SGPRs.

That led me to invent this solution that abuses the image descriptor.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák ddd33431c5 radeonsi: clean up aniso state translation 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák f7420ef5b4 radeonsi: enable some sampler fields to match the closed driver 
copied from the Vulkan driver

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák 1a98be001f gallium/radeon: fix maximum texture anisotropy setup 
We were overdoing it for non-power-of-two values.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák 2d7be5d37e gallium/radeon: never choose a linear tiling for DB surfaces 
Just for consistency. This is actually not a problem, because both addrlib
and radeon check and fix this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák b7878146c4 gallium/radeon: removing dead code for sharing stencil buffers 
This is a remnant of the times when the DDX was allocating depth-stencil
buffers for windows. Now, st/dri allocates them and doesn't share them.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák 73aeebd772 radeonsi: allow clearing buffers >= 4 GB 
Only CMASK and DCC clears can use this, because only textures can be so
large.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák 1dd8832e04 gallium/radeon: allow allocating textures >= 4 GB 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:48 +02:00
Marek Olšák 0689741e51 winsys/radeon: fix printing allocation failures 
print as unsigned instead of signed

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:47 +02:00
Marek Olšák 0ba0933f48 winsys/amdgpu: add support for 64-bit buffer sizes 
v2: fail in radeon_winsys_bo_create if size > 32 bits

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:47 +02:00
Marek Olšák 7e78b5ed38 pb_buffer: switch pb_buffer::size to 64 bits 
being able to allocate more than 4 GB may be useful

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:47 +02:00
Marek Olšák e241a63512 gallium/radeon: remove R600_QUERY_HW_FLAG_TIMER 
not used anymore

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:47 +02:00
Marek Olšák 0222351fc1 gallium/radeon: merge timer and non-timer query lists 
All of them are paused only between IBs.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:47 +02:00
Marek Olšák 7347c068d8 r600g: don't manually stop queries for blitter 
r600_set_active_query_state does it better.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:47 +02:00
Marek Olšák 12fee5b93e r600g: add pausing pipeline & streamout queries into set_active_query_state 
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:47 +02:00
Marek Olšák e90fe60b72 r600g: implement set_active_query_state for pausing occlusion queries 
Use ZPASS_INCREMENT_DISABLE everywhere.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:47 +02:00
Marek Olšák 5248676f87 r600g: simplify r600_set_occlusion_query_state 
The caller does the same checking.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:47 +02:00
Marek Olšák b82893f93a gallium/radeon: move pipeline stat context flags to common code 
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:47 +02:00
Marek Olšák aa79a3269f r600g: fix typo in r600 register definitions 
Acked-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
 2016-04-12 14:29:47 +02:00
Marek Olšák a4c288d8e1 gallium/radeon: unify checking streamout enable state 
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:47 +02:00
Marek Olšák 466aa57185 radeonsi: fix mask checking when emitting scissors and viewports 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
 2016-04-12 14:29:46 +02:00
Marek Olšák f3eebb84eb radeonsi: implement and rely on set_active_query_state 
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:46 +02:00
Marek Olšák e599b8f384 gallium: pause queries for all meta ops 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:46 +02:00
Marek Olšák 26171bd67e gallium: add pipe_context::set_active_query_state for pausing queries 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2016-04-12 14:29:46 +02:00
Bas Nieuwenhuizen fc67375379 radeonsi: Synchronize a streamout write after read hazard. 
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2016-04-12 13:55:38 +02:00
Hans de Goede dccdb655a1 nv30: Add missing PIPE_SHADER_CAP_INTEGERS to get_shader_param() 
Add missing PIPE_SHADER_CAP_INTEGERS for frag shaders to
nv30_screen_get_shader_param().

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
 2016-04-12 11:41:12 +02:00
Haixia Shi b0e3ba61b5 dri/i965: extend GLES3 sRGB workaround to cover all formats 
It is incorrect to assume BGRA byte order for the GLES3 sRGB workaround.

v2: use _mesa_get_srgb_format_linear to handle all formats

Signed-off-by: Haixia Shi <hshi@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2016-04-12 02:06:12 -07:00
Eduardo Lima Mitev ea8a65f503 i965: Add autogenerated 'brw_nir_trig_workarounds.c' to gitignore 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2016-04-12 10:44:19 +02:00
Rhys Kidd 703c1e69d8 glsl: Update hash table comments in constant propagation 
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2016-04-12 01:29:19 -07:00
Dave Airlie afa8707ba9 softpipe: add SSBO/shader atomics support. 
This adds support for the features requires for ARB_shader_storage_buffer_object
and ARB_shader_atomic_counters, ARB_shader_atomic_counter_ops.

[airlied: some cleanups applied]
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
 2016-04-12 14:16:13 +10:00
Dave Airlie c2aeeca455 draw: add support for passing buffers to vs/gs shaders. 
Like the image code, but for shader buffers this time.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
 2016-04-12 14:15:36 +10:00
Dave Airlie 081a958bcd tgsi: add support for buffer/atomic operations to tgsi_exec. 
This adds support for doing load/store/atomic operations on
buffer objects.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
 2016-04-12 14:15:33 +10:00
Dave Airlie 9c7a0d188a tgsi: set nonhelpermask for vertex shaders 
For atomic operations we really need to avoid executing unnecessary shaders, so for some
tests that just draw a single point we only want one vertex to get processed not 4,

this fixes a number of the atomic counters tests.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
 2016-04-12 14:15:16 +10:00
Ian Romanick 193a5cee6a nir: Fix typo in comment 
Trivial.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
 2016-04-11 19:24:19 -07:00
Markus Wick 18c8b927e2 nir: Merge redudant integer clamping. 
Dolphin uses them a lot. Range tracking would be better in the long term,
but this two lines works fine for now.

Signed-off-by: Markus Wick <markus@selfnet.de>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
 2016-04-11 18:48:50 -07:00
Kenneth Graunke bfd17c76c1 i965: Port INTEL_PRECISE_TRIG=1 to NIR. 
This makes the extra multiply visible to NIR's algebraic optimizations
(for constant reassociation) as well as constant folding.  This means
that when the result of sin/cos are multiplied by an constant, we can
eliminate the extra multiply altogether, reducing the cost of the
workaround.

It also means we only have to implement it one place, rather than in
both backends.

This makes INTEL_PRECISE_TRIG=1 cost nothing on GPUTest/Volplosion,
which has a ton of sin() calls, but always multiplies them by an
immediate constant.  The extra multiply gets folded away.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
 2016-04-11 18:44:17 -07:00
Kenneth Graunke b0dffdc616 i965: Pass brw_compiler into brw_preprocess_nir() instead of is_scalar. 
I want to be able to read other fields.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
 2016-04-11 18:44:12 -07:00