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Alyssa Rosenzweig afa20a840b asahi: Set uniform counts accurately 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 15:00:04 -04:00
Alyssa Rosenzweig ec9eae99b1 agx: Report GPRs to the driver 
This needs to be passed onto the hardware.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 15:00:01 -04:00
Alyssa Rosenzweig 6e32826345 agx: Avoid reading high uniforms from device_load 
This does not seem to be possible architecturally. Exhaustively checked
all bits of the encoding. Avoids regressing

dEQP-GLES3.functional.texture.units.8_units.only_2d.0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:59 -04:00
Alyssa Rosenzweig 5bd245d2cd agx: Handle 64-bit moves 
lower_resinfo generates some 64-bit math, so we need to handle it. Even
though we don't have native 64-bit moves, it's convenient to pretend we
do to avoid special cases in the IR. In particular, modelling 64-bit
mov_imm in the IR means our existing small constant propagation code
works, with zero-extension from 8->64.

Fixes dEQP-GLES3.functional.texture.units.2_units.only_2d_array.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:52 -04:00
Alyssa Rosenzweig 1521d9c58c agx: Restrict copyprop of uniforms 
Some instructions don't accept uniform registers as sources (yet?),
avoid this hazard in the optimizer.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:51 -04:00
Alyssa Rosenzweig cef13f8ab1 agx: Handle uniforms passed to COLLECT 
It's useful to be able to copyprop uniform registers into COLLECT. That
requires handling of uniform registers in the parallel copy lowering,
which isn't too hard to add.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:48 -04:00
Alyssa Rosenzweig 056280a4a1 agx: Implement scalar load/store_preamble 
These need to copy values between GPRs and uniform registers. This is pretty
easy in either direction. This implements scalar versions of the intrinsics. A
backend NIR pass will scalarize for us.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:46 -04:00
Alyssa Rosenzweig 14fe5bc598 agx: Strengthen assert for packing ld/st instructions 
We really need to autogenerate the packing code... It's on the todo
list, currently in discussions on how to best go about this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:44 -04:00
Alyssa Rosenzweig 41b54d4a58 agx: Allow larger indices for ld/st 
For memory load/store instructions, the immediate is 16-bit, not 8-bit
like for ALUs.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:43 -04:00
Alyssa Rosenzweig 05009d1dad agx: Add uniform_store instruction 
Moves data from GPRs to uniform registers. Encoded like load/store
instructions, so reuse the device_load packing code.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:40 -04:00
Alyssa Rosenzweig ca4fe9d3f5 agx: Align preamble shaders 
I don't know if it's ok to have unaligned programs, let's not risk it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:38 -04:00
Alyssa Rosenzweig e466a7d1d8 agx: Handle multiple functions 
Needed for preambles. Make agx_context map to nir_function_impl and
the (out, key, binary) triple the only global shader state.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:36 -04:00
Alyssa Rosenzweig af74e746cd agx: Make push_count public 
The driver needs to plumb this information into the hardware. It will
also make it easier to preserve across preamble/main function in a
moment.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:34 -04:00
Alyssa Rosenzweig 2d63864e03 agx: Check that we don't push too much 
Currently we don't have a good mechanism for this other than being
careful... assert() at least. The long term plan is to lift the
UBO/VBO lowerings into NIR, making the sysval requirements visible in
the NIR. (And possibly moving to a descriptor set model to better match
Vulkan? I need to talk to jekstrand about what we want to do here long
term.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:32 -04:00
Alyssa Rosenzweig c74d6c4f9e agx: Be less sloppy about high uniforms 
We need 9-bits to index into the uniform file. Fix an overflow and add
some asserts to try to catch these issues earlier.

Sigh, C.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:29 -04:00
Alyssa Rosenzweig a0da23d520 asahi: Support preamble shaders 
Extend the compiler/driver ABI to attach preambles, and plumb them into
the USC hardware when needed. This is the easy part!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:27 -04:00
Alyssa Rosenzweig 9061e960b2 asahi: Add group tests 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:25 -04:00
Alyssa Rosenzweig 8b464f4c59 asahi: Don't use unnecessary test fixture 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:23 -04:00
Alyssa Rosenzweig 537a77ea6b asahi: Rename LOD clamps tests to fit other packing 
We'll use for testing the "groups" encoding.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:59:21 -04:00
Alyssa Rosenzweig 6195ac93d6 asahi: Use USC_UNIFORM_HIGH 
Abstract it away so we get access to the full uniform file without
special cases.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:58:53 -04:00
Alyssa Rosenzweig 348ac0f4a2 asahi: Make agx_varyings a union 
More accurate.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:58:51 -04:00
Alyssa Rosenzweig 721c4f2186 asahi: Remove "padding" field 
Trivial.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:58:48 -04:00
Alyssa Rosenzweig 06cb242a54 asahi: Identify more shader-related fields 
The big discovery is the "number of uniform registers" field. I learned
about this one accidentally when my preamble shaders weren't working
right, because we had inadvertently hardcoded "at most 32 registers" :-)

In the course of identifying that field, I found that the pipeline
address is used as a tagged pointer, with some unknown field in the
bottom bits and alignment demanded. The XML is updated to account for
this.

I later found that there's also a "number of general purpose registers
used by the preamble shader" field. I missed this one first, because the
encoding is slightly different from the usual "number of general purpose
registers in the main shader" field. The specification is slightly
coarser. I don't know why the hardware needs that
information anyway -- occupancy of the preamble shader should be
irrelevant -- but it's not a big deal.

Finally I found that the "more than 4 textures?" bit is... not that. I
do not yet know what it is, but it is... not that.

These all use the new groups() modifier for GenXML

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:58:37 -04:00
Alyssa Rosenzweig 24bfa5af88 asahi: Identify "Uniform high" USC word 
The start field in the Uniform USC word is only 8-bits, whereas 9-bits
are required to address the entire uniform register file. This other
word gets used for the high half, with start indexed from u128l in
the natural way.

Apparently spending the evening stuffing too many uniforms into Metal is
paying off.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:54:07 -04:00
Alyssa Rosenzweig 0e1f9ca9f6 asahi: Route shader-db stats to debug callback 
This way multithreading works correctly in shader-db including CPU time account.
Code from v3d via panfrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:54:07 -04:00
Alyssa Rosenzweig e126338394 asahi: Precompile for shader-db 
This gets shader-db's runner working, in conjunction with a shader-db ./run
modified to set ASAHI_MESA_DEBUG=precompile. This flag triggers precompiles of
all shaders witha default key so we can exercise the compiler.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:54:07 -04:00
Alyssa Rosenzweig 46ae8e659d asahi: Remove AGX_FAKE_DEVICE environment variable 
The proper way to fake a device on Linux will be drm-shim.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:54:07 -04:00
Alyssa Rosenzweig 13e90bebe1 agx: Remove command line compiler 
It has not been used in quite some time but adds maintainence burden.
Its function is replaced by drm-shim in conjunction with shader-db's
./run, which goes through the actual driver.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:54:07 -04:00
Alyssa Rosenzweig 80de33cf6a nir/opt_preamble: Move load_texture_base_agx 
nir_opt_preamble will be crucial to optimize out the lowering for array
textures on AGX, which involves this AGX-specific sysval.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
 2022-10-22 14:48:04 -04:00
Alyssa Rosenzweig ba551d293f asahi: Hold a reference to BOs in a batch 
Fixes GPU-side use after frees, e.g. in dEQP-GLES2.functional.texture.vertex.2d.wrap.clamp_mirror

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19215>
 2022-10-22 13:52:53 +00:00
Georg Lehmann 741dbadae0 nir: Fix ifind_msb_rev constant folding. 
For example if src0 is 0x80000000 we should return 1, not 0.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

Fixes: a5747f8ab3 ("nir: add opcodes for *find_msb_rev and lowering")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18951>
 2022-10-22 11:57:55 +02:00
Georg Lehmann 125741dbae nir/opt_algebraic: Optimize various find_msb_rev patterns. 
From dxvk, dxil-spirv, fxc, dxc and others.

Totals from 177 (0.13% of 134913) affected shaders:
CodeSize: 1079504 -> 1059872 (-1.82%)
Instrs: 195381 -> 192269 (-1.59%)
Latency: 3664137 -> 3631951 (-0.88%)
InvThroughput: 599479 -> 585675 (-2.30%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18951>
 2022-10-22 11:57:33 +02:00
Georg Lehmann d57f5c9cac radv,aco: Lower uclz in NIR. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18951>
 2022-10-22 11:57:23 +02:00
Georg Lehmann 7505be3497 nir/opt_algebraic: Add an option to lower uclz. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18951>
 2022-10-22 11:57:10 +02:00
Georg Lehmann 049b60cf4b ac/llvm: Implement [ui]find_msb_rev. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18951>
 2022-10-22 11:57:06 +02:00
Georg Lehmann 058174c4de aco: Implement [ui]find_msb_rev. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18951>
 2022-10-22 11:57:00 +02:00
Georg Lehmann 1e552b9c95 nir/opt_algebraic: Mirror optimizations for find_msb_rev. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18951>
 2022-10-22 11:56:44 +02:00
Konstantin Seurer b5ecb5388e radv/rt: Fix setting tmax for opaque AABBs 
data->vars->tmax will be overwritten by inner_vars.tmax so we have to
set inner_vars.tmax instead. This probably doesn't affect anything in
practise.

cc: mesa-stable

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19207>
 2022-10-22 08:55:58 +00:00
Emma Anholt 22f7f167cd nir/opt_phi_precision: Fix missing swizzles when narrowing phi srcs. 
This NIR:

	vec4 32 ssa_169 = phi block_1: ssa_168, block_2: ssa_138
	vec1 16 ssa_209 = f2fmp ssa_169.x
	vec1 16 ssa_210 = f2fmp ssa_169.y
	vec1 16 ssa_211 = f2fmp ssa_169.z
	vec1 16 ssa_212 = f2fmp ssa_169.w
	vec4 16 ssa_213 = vec4 ssa_209, ssa_210, ssa_211, ssa_212
	intrinsic store_output (ssa_213, ssa_171) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float16 /*144*/, io location=4 slots=1 mediump /*8388740*/, xfb() /*0*/, xfb2() /*0*/)

would turn into:

	vec4 32 ssa_169 = phi block_1: ssa_168, block_2: ssa_138
	vec4 16 ssa_216 = phi block_1: ssa_214, block_2: ssa_215
	vec1 16 ssa_209 = f2fmp ssa_169.x
	vec1 16 ssa_210 = f2fmp ssa_169.y
	vec1 16 ssa_211 = f2fmp ssa_169.z
	vec1 16 ssa_212 = f2fmp ssa_169.w
	vec4 16 ssa_213 = vec4 ssa_216.x, ssa_216.x, ssa_216.x, ssa_216.x
	intrinsic store_output (ssa_213, ssa_171) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float16 /*144*/, io location=4 slots=1 mediump /*8388740*/, xfb() /*0*/, xfb2() /*0*/)

ignoring the swizzles from the f2fmp srcs.  Fixes failures in
dEQP-GLES2.functional.shaders.random.all_features.fragment.20 on
turnip+ANGLE.

Fixes: c7b935962b ("nir: Add pass to lower phi precision")
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19179>
 2022-10-22 03:06:31 +00:00
Yonggang Luo 783b416e65 ci/macos: Building both dri and xlib version of glx 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19221>
 2022-10-22 01:34:53 +00:00
Yonggang Luo 6c9f8d8662 xlib: Remove macro guard with GLX_INDIRECT_RENDERING in xlib.c 
According meson about with_glx == 'xlib' check only defied '-DUSE_XSHM',
so the macro check GLX_INDIRECT_RENDERING make no-sense, removed it.

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19221>
 2022-10-22 01:34:53 +00:00
Yonggang Luo 5bed3d4ad6 meson: with_glx never assigned to 'gallium-xlib', remove 'gallium-xlib' 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19221>
 2022-10-22 01:34:53 +00:00
Yonggang Luo 814682d00c meson: with_glx never assigned to 'gallium-xlib', so need add with_glx == 'xlib' for dep_glproto 
Fixes: 76791db088 ("mesa/x11: Remove the swrast-classic-based fake libGL")

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19221>
 2022-10-22 01:34:53 +00:00
Thomas H.P. Andersen 9a7e93f1f6 vulkan: drop const for descriptor set 
drivers should be able to update the reference count
member of the vk_descriptor_set_layout struct

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19132>
 2022-10-21 22:36:45 +00:00
Mike Blumenkrantz 5aa437a9f1 zink: fix ds3 line stipple enable handling 
ds3 can be used without line stipple enable if the driver doesn't support
line stipple, so this needs special-casing

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19204>
 2022-10-21 21:27:13 +00:00
Mike Blumenkrantz 12fded5965 zink: fix duplicate VK_DYNAMIC_STATE_LINE_STIPPLE_EXT setting 
if ds3 is used, this is already set above

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19204>
 2022-10-21 21:27:13 +00:00
Alyssa Rosenzweig 9de7e49e6f panfrost: Remove NIR_SERIALIZED support 
Only used by Clover (due to the dynamic pipeloader), which we never
shipped support for. We'll do OpenCL via Rusticl, which does not use the
dynamic pipeloader.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18972>
 2022-10-21 21:12:14 +00:00
Rhys Perry dfce433385 aco/gfx11: optimize LS/HS load_local_invocation_index 
fossil-db (gfx1100):
Totals from 1361 (1.01% of 135032) affected shaders:
Instrs: 501227 -> 500469 (-0.15%); split: -0.16%, +0.01%
CodeSize: 2730012 -> 2724820 (-0.19%); split: -0.20%, +0.00%
VGPRs: 63716 -> 63688 (-0.04%)
Latency: 2228848 -> 2228858 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 878418 -> 878275 (-0.02%); split: -0.02%, +0.00%
VClause: 14866 -> 14868 (+0.01%); split: -0.03%, +0.04%
SClause: 16674 -> 16645 (-0.17%); split: -0.22%, +0.05%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19196>
 2022-10-21 20:01:30 +00:00
Rhys Perry 8c716525cf ac/llvm: ignore g16 if the image opcode doesn't use derivatives 
g16 is irrelevant in this case.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19198>
 2022-10-21 19:09:49 +00:00
Rhys Perry c492779924 ac/llvm: fix mixing non-uniform/uniform sampler/texture descriptors 
Non-uniform descriptors are not loaded in NIR and instead the pointer is
passed to abi->load_sampler_desc. It can be the case that only the texture
or sampler uses this path.

For the descriptor which doesn't use the path, we would previously pass
NULL to abi->load_sampler_desc.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19198>
 2022-10-21 19:09:49 +00:00