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181801 Commits

Author SHA1 Message Date
Rob Clark
753c8bf834 freedreno/a6xx: Emit CP_SET_AMBLE packets 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Rob Clark
d572fcf04a freedreno/a6xx: Move more state emit per-bin 
With skipsaverestore=1 we can't rely on this values being restored.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Rob Clark
270e595811 freedreno/a6xx: Move static regs to preamble IB 
We can re-use this for preemption.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Rob Clark
0c36ca7446 freedreno/a6xx: Move PC_TESSFACTOR_ADDR emit 
This depends on batch state, so emit in gmem code.  The remainder of the
static reg initialization can be re-used across batches.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Rob Clark
f3cc9335e6 freedreno/a6xx: Set bin size per bin 
It is not saved/restored by level 1 preemption with skipsaverestore=1,
so we need to set it for each bin.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Rob Clark
be6342633c freedreno/a6xx: Cleanup WFIs around RB_CCU_CNTL 
This was only actually needed on the earliest a6xx (probably just
a630?).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Rob Clark
3aac51a6d5 freedreno/a6xx: De-open-code VFD_MODE_CNTL 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Rob Clark
2f82555efa freedreno/a6xx: Only emit VFD/PC_POWER_CNTL for a6xx 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Connor Abbott
c7a7f6dad8 tu: Add TU_DEBUG=hiprio 
The same as FD_MESA_DEBUG=hiprio in freedreno.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Connor Abbott
1d2b479a3b tu: Allow being preempted on a7xx 
This is only tested on a7xx so far, although it should work on a6xx too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Connor Abbott
3631f9ad62 tu/virtio: Make virtio_simple_ioctl take a vdrm_device 
We need to do an ioctl in order to try to create a queue before the
tu_device is created.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Connor Abbott
700e26a448 tu: Emit CP_SET_AMBLE packets 
Make sure skipsaverestore works.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Connor Abbott
db86c4c496 tu: Simplify device startup CS creation 
We have a few different command streams we create at startup. Simplify
the initialization by creating a single sub_cs to allocate all of the
cs's out of and inlining structures where appropriate.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:46 +00:00
Connor Abbott
acdbfe9812 tu: Re-emit LRZ state before each bin 
Similar to the bin size register, even though this is the same for each
bin it needs to be re-emitted to make skipsaverestore work.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:45 +00:00
Connor Abbott
b9d9fdb6d1 tu: Write bin size for each bin 
While the register is constant for all bins in the render pass, it is
not saved and restored with level 1 preemption with skipsaverestore=1 so
it needs to be restored. Follow what the blob does and set it before
each bin.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:45 +00:00
Connor Abbott
4d75a4ac4b tu: Split out register setting from tu6_init_hw() 
Split out the parts that will also have to be done in the bin restore
IB.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:45 +00:00
Connor Abbott
a9f88ff2af tu: Don't WFI after initializing RB_CCU_CNTL on a7xx 
There's no reason to do this and the blob doesn't.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:45 +00:00
Jonathan Marek
b6432a6c66 freedreno/a6xx: add missing USES_GMEM flag and BIN_RENDER_END markers 
Add USES_GMEM flag to indicate that GMEM is in use, so that preemption can
know it needs save and restore GMEM contents.

The missing BIN_RENDER_END markers are also added, their purpose is to
clear the USES_GMEM flag once GMEM is no longer in use.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:45 +00:00
Jonathan Marek
72900e1aac freedreno: improve a6xx CP_SET_MARKER xml definition 
Use real names for most of a6xx_marker enum, add USES_GMEM, remove
overlapping bitfields.

Note the actual "real names" start with PM4_RENDER_MODE_ instead of RM6_

This is a small change to adreno_pm4.xml, with the corresponding
find/replace and updated ci references

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
 2024-10-10 00:50:45 +00:00
Connor Abbott
022fb8e4c7 ir3, turnip: Support VK_*_compute_shader_derivatives on a7xx 
Quad derivative groups are supported since a7xx using the tiling mode
bit. Linear derivative groups may also work on a6xx but I haven't tested
it yet.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31130>
 2024-10-10 00:14:04 +00:00
Lionel Landwerlin
624d83bfd1 isl: add support of aux disable bit on hiz 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
 2024-10-09 23:38:19 +00:00
Lionel Landwerlin
e4d1fd7fd6 iris: delete stencil mapping support 
Now that we have ISL support.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
 2024-10-09 23:38:19 +00:00
Lionel Landwerlin
1a72fc013c isl: Tile W memcpy support 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
 2024-10-09 23:38:19 +00:00
Lionel Landwerlin
c0e98d2c89 isl/tests: rename span variable to xt_sub_range_alignment 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
 2024-10-09 23:38:19 +00:00
Lionel Landwerlin
e44249af5d isl/tests: add more coordinates for full tiles testing 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
 2024-10-09 23:38:19 +00:00
Lionel Landwerlin
52263413f4 isl: remove duplicated copy for tileX/TileY 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
 2024-10-09 23:38:19 +00:00
Gurchetan Singh
635cefcdad gfxstream: use sync_fence_info 
This gives logs of the form:

[bootanimation] Fence: bbq-adapter#0(BLAST Consumer:0, status: 1, timestamp (ms): 15391

sync_merge(..) allows userspace to name the fence
and that's what's observed for in-fences.  The goal
is debug potentially long-running fences via the
use of timestamp data.

Perfetto may be used too.

Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31548>
 2024-10-09 22:53:05 +00:00
Gurchetan Singh
d7f264452e util: add sync_fence_info 
This returns sync file info, including timestamps.
The caller is responsible for freeing the memory.

Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31548>
 2024-10-09 22:53:05 +00:00
Gurchetan Singh
02b383fded gfxstream: use util/libsync 
Gets rid of some #ifdefs.

Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31548>
 2024-10-09 22:53:05 +00:00
Gurchetan Singh
34e0394580 gfxstream: nuke util function 
Use ALIGN_POT instead.

Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31548>
 2024-10-09 22:53:05 +00:00
Gurchetan Singh
5b82c130d9 gfxstream: add clang-format 
Version of clang from the gfxstream
repo.

Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31548>
 2024-10-09 22:53:05 +00:00
Danylo Piliaiev
b31a4037de tu/a750: Workaround GPU fault when fast-clearing R8G8 formats 
Clearing VK_FORMAT_R8G8_* with fast-clear value and certain
dimensions (e.g. 960x540), and having GMEM renderpass afterwards
may lead to a GPU fault on A7XX.

Prop driver directly clears UBWC layers for R8G8_UNORM, and
doesn't use UBWC for R8G8_UINT. It uses generic clear for R8G8 only
for renderpass, where doesn't cause issues in Turnip.

Fixes GPU fault in Limbo game running via Zink.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31258>
 2024-10-09 22:01:10 +00:00
Samuel Pitoiset
1641db461f radv: fix generating the global key for pipeline binaries 
The global key wasn't considering GPU family, Git revision etc and it
was mostly invariant.

Fixes: be06bfcbed ("radv: add initial support for pipeline binaries")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11995
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31576>
 2024-10-09 21:15:48 +00:00
Maíra Canal
47a78614ea v3d: Don't use performance counters names array with an older kernel 
Starting with Linux v6.11+, performance counter information is no
longer duplicated in both the kernel and userspace. Instead, an IOCTL
retrieves this information, allowing userspace to maintain a local
array for reuse, thus avoiding redundant kernel queries.

However, support for older kernels without these new IOCTLs remains.
To distinguish between versions, we check `devinfo->max_perfcnt` -
which is non-zero on Linux v6.11+ and zero on older kernels.

Currently, applications using performance queries on platforms with
older kernels encounter a SEGFAULT, as we don't validate
`devinfo->max_perfcnt` before accessing the userspace array for
performance counter information.

This commit makes sure that, if `devinfo->max_perfcnt` is zero,
`screen->perfcnt_names` will be NULL. This way, we can check if
`screen->perfcnt_names` is different than NULL before attempting to use
the userspace array.

Fixes: 017dde0d1c ("v3d: Use DRM_IOCTL_V3D_GET_COUNTER to get perfcnt information")
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31552>
 2024-10-09 15:51:51 -03:00
Zhang He
5d7f3753d7 iris, crocus: fix a typo and break comment line correctly 
Signed-off-by: Zhang He <zhanghe9702@163.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31557>
 2024-10-09 17:56:23 +00:00
Christian Gmeiner
04521c14b0 etnaviv: Improve split sampler check 
Check if the block size is bigger then 64. We want to block
e.g. one of the following formats:
 - R32G32B32A32_FLOAT
 - R32G32B32A32_SINT
 - R32G32B32A32_ZINT

Unbreaks e.g. dEQP-GLES3.functional.fbo.completeness.renderable.texture.color0.rgb16i

Fixes: e481c1269c ("etnaviv: disable 64bpp render/sampler formats")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27111>
 2024-10-09 15:17:33 +00:00
Juan A. Suarez Romero
992ada2f8f v3d: add new flake 
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31572>
 2024-10-09 09:17:36 +02:00
Samuel Pitoiset
336f80137d radv: fix conditional rendering with DGC preprocessing on compute 
Preprocess now must use the same conditional rendering state as the
execute, so the DGC prepare shader must reset the number of sequences
to generate an empty cmdbuf for compute.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31563>
 2024-10-08 12:35:16 -04:00
David Rosca
89ea2b6c26 radeonsi/vcn: Don't hardcode nal_ref_idc 
For slice header use the value parsed by frontend.
For SPS and PPS directly output first NAL byte from packed header.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31354>
 2024-10-08 15:24:36 +00:00
David Rosca
8880f0f141 radeonsi/vcn: Use correct initial DPB size for HEVC encode 
sps_max_dec_pic_buffering_minus1 specifies the maximum number of
references, same as H264 max_num_ref_frames.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31354>
 2024-10-08 15:24:36 +00:00
David Rosca
88c134d496 radeonsi/vcn: Allow per-frame QP and max frame size changes 
Also don't reset QP values when rate control changes because
QP is ignored with rate control enabled anyway.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31354>
 2024-10-08 15:24:36 +00:00
Rob Clark
85d7826afa freedreno/ir3: Add more cat1 float-immed cases 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31446>
 2024-10-08 13:50:05 +00:00
Rob Clark
8ddfe9cfc8 freedreno/ir3: Fix cat1 parser ambiguity vs FLUTs 
The lexer can't really tell the difference.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31446>
 2024-10-08 13:50:05 +00:00
Rob Clark
0633a23dc9 freedreno/ir3: Add half-FLUT cases 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31446>
 2024-10-08 13:50:05 +00:00
Rob Clark
771fe03787 freedreno/ir3: Fix GPU name in disasm test 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31446>
 2024-10-08 13:50:05 +00:00
Lucas Stach
a422ebc500 etnaviv: flush shader caches when UBO content is modified 
Shader load/stores are cached by the shader L1 cache. As UBOs on etnaviv
are implemented as regular loads from the constant buffer, this cache
needs to be flushed whenever the content of a constant buffer is modified.

Fixes most of the currently failing dEQP-GLES3.functional.ubo.* on GC3000.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31527>
 2024-10-08 10:32:16 +00:00
Tapani Pälli
78b614b333 anv: add depth, DC and L3 fabric flush for aux map invalidation 
These should be included according to table in Bspec 43904.

Patch removes PIPE_CONTROL_STATE_CACHE_INVALIDATE based on HSDES.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
 2024-10-08 08:45:40 +00:00
Tapani Pälli
3e29ea69ce iris: add depth, DC and L3 fabric flush for aux map invalidation 
These should be included according to table in Bspec 43904.

Patch removes PIPE_CONTROL_STATE_CACHE_INVALIDATE based on HSDES.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
 2024-10-08 08:45:40 +00:00
Tapani Pälli
11774075a3 iris: add plumbing/support for L3 fabric flush 
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
 2024-10-08 08:45:40 +00:00
Tapani Pälli
e3814dee1a anv: add plumbing/support for L3 fabric flush 
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
 2024-10-08 08:45:40 +00:00