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radeonsi/vcn: Don't hardcode nal_ref_idc

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For slice header use the value parsed by frontend.
For SPS and PPS directly output first NAL byte from packed header.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31354>
This commit is contained in:
David Rosca
2024-09-24 08:38:00 +02:00
committed by Marge Bot
parent 8880f0f141
commit 89ea2b6c26
3 changed files with 14 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeonsi/radeon_vcn_enc.c
+5 -2
View File
@@ -1490,11 +1490,14 @@ static uint32_t radeon_vcn_enc_encode_h264_header(struct radeon_encoder *enc,
struct pipe_enc_raw_header *header,
uint8_t *out)
{
/* Startcode may be 3 or 4 bytes. */
const uint8_t nal_byte = header->buffer[header->buffer[2] == 0x1 ? 3 : 4];
switch (header->type) {
case PIPE_H264_NAL_SPS:
return radeon_enc_write_sps(enc, out);
return radeon_enc_write_sps(enc, nal_byte, out);
case PIPE_H264_NAL_PPS:
return radeon_enc_write_pps(enc, out);
return radeon_enc_write_pps(enc, nal_byte, out);
default:
assert(header->buffer);
memcpy(out, header->buffer, header->size);
src/gallium/drivers/radeonsi/radeon_vcn_enc.h
+2 -2
View File
@@ -346,9 +346,9 @@ void radeon_enc_4_0_init(struct radeon_encoder *enc);
void radeon_enc_5_0_init(struct radeon_encoder *enc);
unsigned int radeon_enc_write_sps(struct radeon_encoder *enc, uint8_t *out);
unsigned int radeon_enc_write_sps(struct radeon_encoder *enc, uint8_t nal_byte, uint8_t *out);
unsigned int radeon_enc_write_pps(struct radeon_encoder *enc, uint8_t *out);
unsigned int radeon_enc_write_pps(struct radeon_encoder *enc, uint8_t nal_byte, uint8_t *out);
unsigned int radeon_enc_write_vps(struct radeon_encoder *enc, uint8_t *out);
src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
+7 -10
View File
@@ -191,7 +191,7 @@ static void radeon_enc_quality_params(struct radeon_encoder *enc)
RADEON_ENC_END();
}
unsigned int radeon_enc_write_sps(struct radeon_encoder *enc, uint8_t *out)
unsigned int radeon_enc_write_sps(struct radeon_encoder *enc, uint8_t nal_byte, uint8_t *out)
{
struct radeon_enc_pic *pic = &enc->enc_pic;
struct pipe_h264_enc_seq_param *sps = &pic->h264.desc->seq;
@@ -200,7 +200,7 @@ unsigned int radeon_enc_write_sps(struct radeon_encoder *enc, uint8_t *out)
radeon_enc_set_output_buffer(enc, out);
radeon_enc_set_emulation_prevention(enc, false);
radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
radeon_enc_code_fixed_bits(enc, 0x67, 8);
radeon_enc_code_fixed_bits(enc, nal_byte, 8);
radeon_enc_byte_align(enc);
radeon_enc_set_emulation_prevention(enc, true);
radeon_enc_code_fixed_bits(enc, pic->spec_misc.profile_idc, 8);
@@ -454,13 +454,13 @@ unsigned int radeon_enc_write_sps_hevc(struct radeon_encoder *enc, uint8_t *out)
return enc->bits_buf_pos;
}
unsigned int radeon_enc_write_pps(struct radeon_encoder *enc, uint8_t *out)
unsigned int radeon_enc_write_pps(struct radeon_encoder *enc, uint8_t nal_byte, uint8_t *out)
{
radeon_enc_reset(enc);
radeon_enc_set_output_buffer(enc, out);
radeon_enc_set_emulation_prevention(enc, false);
radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
radeon_enc_code_fixed_bits(enc, 0x68, 8);
radeon_enc_code_fixed_bits(enc, nal_byte, 8);
radeon_enc_byte_align(enc);
radeon_enc_set_emulation_prevention(enc, true);
radeon_enc_code_ue(enc, 0x0); /* pic_parameter_set_id */
@@ -608,12 +608,9 @@ static void radeon_enc_slice_header(struct radeon_encoder *enc)
radeon_enc_set_emulation_prevention(enc, false);
cdw_start = enc->cs.current.cdw;
if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR)
radeon_enc_code_fixed_bits(enc, 0x65, 8);
else if (enc->enc_pic.not_referenced)
radeon_enc_code_fixed_bits(enc, 0x01, 8);
else
radeon_enc_code_fixed_bits(enc, 0x41, 8);
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* forbidden_zero_bit */
radeon_enc_code_fixed_bits(enc, pps->nal_ref_idc, 2);
radeon_enc_code_fixed_bits(enc, pps->nal_unit_type, 5);
radeon_enc_flush_headers(enc);
instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;