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4663 Commits

Author SHA1 Message Date
Iván Briano 6e5eb0afd3 anv: do not explode on 32 bit builds 
Fixes: 930e862af7 ("anv: add shaders for copying query results")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9213

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23686>
 2023-06-16 22:22:07 +00:00
Tapani Pälli 8f2680871d anv: convert most pc in genX_cmd_buffer to use pc helper 
Some are left, batch_set_preemption does not have devinfo pointer
and IndirectStatePointersDisable does not have corresponding ANV bit.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
 2023-06-16 08:04:20 +00:00
Tapani Pälli 9f3b51255a anv: change most pipe controls in gfx8_cmd_buffer to use pc helper 
One using a flag (PSDSyncEnable) that has no corresponding ANV bit.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
 2023-06-16 08:04:20 +00:00
Tapani Pälli b3589a8899 anv: change pipe control in indirect draw gen to use pc helper 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
 2023-06-16 08:04:20 +00:00
Tapani Pälli 6a7dcd3e12 anv: change pipe controls in genX_gpu_memcpy to use pc helper 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
 2023-06-16 08:04:20 +00:00
Tapani Pälli e70cf3ea98 anv: change pipe control in genX_pipeline to use pc helper 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
 2023-06-16 08:04:20 +00:00
Tapani Pälli c232269db4 anv: change pipe controls in genX_state to use pc helper 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
 2023-06-16 08:04:20 +00:00
Tapani Pälli 6dc95685f3 anv: convert genX_query pipe controls to use pc helper 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
 2023-06-16 08:04:20 +00:00
Tapani Pälli d8c76f8844 anv: implement invalidate part of emit_apply_pipe_flushes with helper 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
 2023-06-16 08:04:20 +00:00
Tapani Pälli 9f6f69e0f9 anv: implement flush part of emit_apply_pipe_flushes with helper 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
 2023-06-16 08:04:20 +00:00
Tapani Pälli c3658f5a5d anv: wrap pipe control emission to a set of helper functions 
This makes it possible to have HW specific rules and WA's implemented
in a central place. Also all pipe controls will get anv_debug_dump_pc.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
 2023-06-16 08:04:20 +00:00
Yiwei Zhang c8d8961f33 anv: avoid requiring ordered memory planes for explicit import 
The spec does not have such requirement, but anv requires it for
validating the offset. However, for DRM_FORMAT_YVU420, chroma channels
can be swapped upon import to match B/R channel order of
VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM.

This fixes some sw codec path in Instagram when interop with gpu.

v2: fix image memory requirement for re-ordered explicit import

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net> (v1)
Reviewed-by: Matt Tuner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23643>
 2023-06-15 17:53:10 +00:00
Erik Faye-Lund a593de7cf3 nir: add missed nir_cmp_imm-helpers 
Seems I missed these in my previous round, let's fix them up now!

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23461>
 2023-06-15 13:34:49 +00:00
Erik Faye-Lund 2a71e332aa nir: use new immediate comparison helpers 
There's plenty of places we can use these new and shiny helpers, so
let's clean up the code a bit.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23460>
 2023-06-15 13:33:58 +02:00
Lionel Landwerlin b3b12c2c27 anv: enable CmdCopyQueryPoolResults to use shader for copies 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
 2023-06-14 09:43:57 +03:00
Lionel Landwerlin e86f3c7abb intel/ds: add query count in query tracepoints 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
 2023-06-14 09:43:57 +03:00
Lionel Landwerlin 930e862af7 anv: add shaders for copying query results 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
 2023-06-14 09:43:57 +03:00
Lionel Landwerlin 4cee8ce7a5 anv: generalize internal kernel concept 
We'll add more of those kernels for other purposes.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
 2023-06-14 09:43:57 +03:00
Lionel Landwerlin 7ca5c84804 anv: add support for simple internal compute shaders 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
 2023-06-14 09:43:57 +03:00
Lionel Landwerlin dbbcd5c32c anv: factor out generation kernel dispatch into helper 
We would like to reuse this mechanism to dispatch different types of
internal shader. Those would replace some of the command streamer
commands we currently use.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
 2023-06-14 09:43:57 +03:00
Lionel Landwerlin 455a13fb7f anv: limit ANV_PIPE_RENDER_TARGET_BUFFER_WRITES to blorp operations using 3D 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
 2023-06-14 09:43:56 +03:00
Lionel Landwerlin d7c28e526b anv: fix incorrect batch for 3DSTATE_CONSTANT_ALL emission 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
 2023-06-14 09:43:56 +03:00
Lionel Landwerlin 0da39bf8ee anv: disable mesh/task for generated draws 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
 2023-06-14 09:43:56 +03:00
Lionel Landwerlin e9c1eaa535 anv: only disable mesh when enabled at the VkDevice level 
Saving ourselves some instructions since it's not going to get used.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23074>
 2023-06-14 09:43:56 +03:00
Lionel Landwerlin efd4a162d3 anv: always report all pipeline stats regardless of stages 
Tools like the scripts in shader-db expect all the fields to be there,
as the stats are put into a CSV file. So just report 0 if a stage
doesn't support workgroup memory size.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23559>
 2023-06-13 23:26:40 +00:00
Lionel Landwerlin 810da51e91 anv: report max simd width only once for fragment shaders 
Reporting the value multiple times is confusing to shader-db scripts
because it believes multiple shaders are affected.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23559>
 2023-06-13 23:26:40 +00:00
Lionel Landwerlin a0a20164eb anv: deal with unsupported VkImageFormatListCreateInfo::pViewFormats 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 697ed61e7c ("anv: Improve image/view usage bits verification")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9190
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23606>
 2023-06-13 20:16:46 +00:00
Tapani Pälli 00a91d8870 anv: use workaround framework for 1408224581, 14014097488 
This makes sure we apply WA only when it is required, these issues
do not happen for later MTL steppings.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23596>
 2023-06-13 13:27:30 +00:00
Rohan Garg d0e0ba897f anv: split ANV_PIPE_RENDER_TARGET_BUFFER_WRITES for finer grained flushing 
split ANV_PIPE_RENDER_TARGET_BUFFER_WRITES into separate CS_STALL,
RT_FLUSH & TILE_FLUSH flags in order to have finer control over cache
coherency.

Tigerlake CS has it's own cache fetching directly from the memory controller,
so we need to do a tile flush to ensure the query data is visible.

This fixes test_resolve_non_issued_query_data in vkd3d on TGL.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Fixes: 3c4c18341a ("anv: narrow flushing of the render target to buffer writes")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23500>
 2023-06-12 14:46:44 +00:00
Lionel Landwerlin 06b436e51e anv: add query tracepoints 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23500>
 2023-06-12 14:46:44 +00:00
Tapani Pälli a4bb6d7c72 anv: remove BDW specific WA for CS stall enable 
This note is in BDW specs but not anymore in gfx9+ specs.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23543>
 2023-06-12 05:58:44 +00:00
Mark Janes 0ce595a89a intel: use generated helpers for Wa_1508744258 
iris_disable_rhwo_optimization can only apply on gfxver 12.0, and has
a version check to that affect.  Add an assertion to warn us if the
workaround ever applies to another version.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21742>
 2023-06-10 00:05:51 +00:00
Filip Gawin fb8c48f4fc anv: allow intel_clflush_range only on igpu 
fixes: 521c216efc
closes: #9106

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23320>
 2023-06-09 21:09:50 +00:00
Hyunjun Ko c39521a929 anv/video: move video requirements to outarray. 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23519>
 2023-06-09 10:07:18 +02:00
Lionel Landwerlin 965503ae22 anv: allow binding tables allocations on compute only queues 
COMPUTE_WALKER is using binding tables.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: eb2b309328 ("anv: defer binding table block allocation to when necessary")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23506>
 2023-06-08 02:37:44 +00:00
Nanley Chery 0c204277e7 intel: Rename the GFX12_CCS_E aux-usage to FCV_CCS_E 
Rename the isl_aux_usage enum to clarify that it is optional on gfx125.

The new name comes from the Alchemist docs, where the feature is
referred to as "Fast Clear Optimization (FCV)".

The rename was done with this command:

   git grep -l "GFX12_CCS_E" | xargs sed -ie "s/GFX12_CCS_E/FCV_CCS_E/g"

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23220>
 2023-06-07 23:39:39 +00:00
Mark Janes d57eedefa9 anv: convert Wa_14010455700 to use workaround mechanism 
The original lineage for 14010455700 is 1808121037.  Use this defect
number to apply the workaround to relevant platforms with the new
workaround mechanism.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23380>
 2023-06-07 22:30:34 +00:00
Yonggang Luo b687fa4ccb vulkan: move nir_convert_ycbcr into vulkan runtime 
This only used by vulkan drivers and depends on vulkan util, so do the move to decouple
nir from vulkan utils

Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23444>
 2023-06-07 08:42:03 +00:00
Alyssa Rosenzweig 99a00e2247 treewide: Use nir_trim_vector more 
Via Coccinelle patches

    @@
    expression a, b, c;
    @@

    -nir_channels(b, a, (1 << c) - 1)
    +nir_trim_vector(b, a, c)

    @@
    expression a, b, c;
    @@

    -nir_channels(b, a, BITFIELD_MASK(c))
    +nir_trim_vector(b, a, c)

    @@
    expression a, b;
    @@

    -nir_channels(b, a, 3)
    +nir_trim_vector(b, a, 2)

    @@
    expression a, b;
    @@

    -nir_channels(b, a, 7)
    +nir_trim_vector(b, a, 3)

Plus a fixup for pointless trimming an immediate in RADV and radeonsi.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23352>
 2023-06-06 18:52:25 +00:00
Tapani Pälli e6e320fc79 anv: make Wa_16013994831 to use intel_needs_workaround 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22560>
 2023-06-06 12:06:22 +00:00
Emma Anholt 0be83bf1c4 anv: Drop unused ALL_GRAPHICS_LIB_FLAGS. 
copy and paste from radv.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22865>
 2023-06-06 09:03:09 +00:00
Erik Faye-Lund 6d142078bc nir: use generated immediate comparison helpers 
This makes the code a bit less verbose, so let's use the helpers.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23393>
 2023-06-05 13:40:08 +00:00
Yonggang Luo 12256136e0 compiler: Rename shader_prim to mesa_prim and replace all usage of pipe_prim_type with mesa_prim 
This is a prepare step to remove depends on p_defines.h in src/util/*

This is done by:
replace pipe_prim_type with mesa_prim
replace shader_prim with mesa_prim
replace PIPE_PRIM_MAX  with MESA_PRIM_COUNT
replace SHADER_PRIM_  with MESA_PRIM_
replace PIPE_PRIM_ with MESA_PRIM_

This patch only replace code only

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23369>
 2023-06-03 03:29:03 +00:00
Dmitry Osipenko 4a2655d084 anv: Use intel_ioctl() helper for GEM_SET_TILING 
Replace opencoded ioctl() usage with a common intel_ioctl() helper.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23399>
 2023-06-02 20:09:24 +00:00
Zhang, Jianxun ec9efee907 anv: Remove alignment to aux ratio on size of main surface 
The existing 4KB alignment is sufficient for both 1MB and
64KB alignment requirements of CCS buffer.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23002>
 2023-06-02 16:50:32 +00:00
Zhang, Jianxun d2b6f16145 anv: Support 1MB AUX mapping (MTL) 
Replace the hardcoded 64KB granularity with a value
provided by AUX module that returns either 64KB(TGL)
or 1MB(MTL) of the running system.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23002>
 2023-06-02 16:50:32 +00:00
José Roberto de Souza 42f707e459 intel: Fix support of kernel versions without DRM_I915_QUERY_ENGINE_INFO 
As Matt Turner pointed out, the commit here fixed breaks in Iris and
ANV in kernel versions without support for DRM_I915_QUERY_ENGINE_INFO.
As compute engines are only present in gfx12 and newer, and support
for DRM_I915_QUERY_ENGINE_INFO was added before any gfx12 platform,
we can check for gfx version before trying to get engine info.

For ANV, this is done by checking if engine_info is not NULL, like in
other places in the ANV source code.

Fixes: a364f23a6c ("intel: Make gen12 URB space reservation dependent on compute engine presence")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9099
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Tested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23257>
 2023-05-31 21:12:10 +00:00
Mark Janes d0669f3ede intel/dev: switch defect identifiers to use lineage numbers 
Update existing workarounds when necessary to match changed
identifiers.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23226>
 2023-05-30 22:13:41 +00:00
Lionel Landwerlin 25c1f325d0 anv: remove unused functions 
I thought I removed those, it seems my rebase got screwed up :(

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 64f20cec28 ("anv: prepare image/buffer views for non indirect descriptors")
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23317>
 2023-05-30 15:14:49 +00:00
Lionel Landwerlin d17af98abc anv: add support for VK_EXT_dynamic_rendering_unused_attachments 
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23294>
 2023-05-30 14:45:49 +00:00