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anv: implement invalidate part of emit_apply_pipe_flushes with helper

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Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
This commit is contained in:
Tapani Pälli
2023-06-15 12:20:45 +03:00
committed by Marge Bot
parent 9f6f69e0f9
commit d8c76f8844
1 changed files with 27 additions and 40 deletions
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src/intel/vulkan/genX_cmd_buffer.c
+27 -40
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@@ -1652,51 +1652,38 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
if (GFX_VER == 9 && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT))
anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe);
anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) {
pipe.StateCacheInvalidationEnable =
bits & ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
pipe.ConstantCacheInvalidationEnable =
bits & ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
#if GFX_VER >= 12
/* Invalidates the L3 cache part in which index & vertex data is loaded
* when VERTEX_BUFFER_STATE::L3BypassDisable is set.
*/
pipe.L3ReadOnlyCacheInvalidationEnable =
bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
#endif
pipe.VFCacheInvalidationEnable =
bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
pipe.TextureCacheInvalidationEnable =
bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
pipe.InstructionCacheInvalidateEnable =
bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT;
#if GFX_VER >= 9 && GFX_VER <= 11
/* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
*
* "Workaround : “CS Stall” bit in PIPE_CONTROL command must be
* always set for GPGPU workloads when “Texture Cache
* Invalidation Enable” bit is set".
*
* Workaround stopped appearing in TGL PRMs.
*/
if (current_pipeline == GPGPU && pipe.TextureCacheInvalidationEnable)
pipe.CommandStreamerStallEnable = true;
/* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
*
* "Workaround : “CS Stall” bit in PIPE_CONTROL command must be
* always set for GPGPU workloads when “Texture Cache
* Invalidation Enable” bit is set".
*
* Workaround stopped appearing in TGL PRMs.
*/
if (current_pipeline == GPGPU &&
(bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT))
bits |= ANV_PIPE_CS_STALL_BIT;
#endif
/* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
*
* "When VF Cache Invalidate is set “Post Sync Operation” must be
* enabled to “Write Immediate Data” or “Write PS Depth Count” or
* “Write Timestamp”.
*/
if (GFX_VER == 9 && pipe.VFCacheInvalidationEnable) {
pipe.PostSyncOperation = WriteImmediateData;
pipe.Address = device->workaround_address;
}
anv_debug_dump_pc(pipe);
uint32_t sync_op = NoWrite;
struct anv_address addr = ANV_NULL_ADDRESS;
/* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
*
* "When VF Cache Invalidate is set “Post Sync Operation” must be
* enabled to “Write Immediate Data” or “Write PS Depth Count” or
* “Write Timestamp”.
*/
if (GFX_VER == 9 && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) {
sync_op = WriteImmediateData;
addr = device->workaround_address;
}
/* Invalidate PC. */
genX(batch_emit_pipe_control_write)(batch, device->info, sync_op, addr,
0, bits);
#if GFX_VER == 12
if ((bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) && device->info->has_aux_map) {
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {