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anv: change pipe controls in genX_state to use pc helper

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Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23583>
This commit is contained in:
Tapani Pälli
2023-06-08 09:32:07 +03:00
committed by Marge Bot
parent 6dc95685f3
commit c232269db4
1 changed files with 21 additions and 22 deletions
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43
src/intel/vulkan/genX_state.c
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@@ -185,14 +185,15 @@ init_common_queue_state(struct anv_queue *queue, struct anv_batch *batch)
*/
if (intel_device_info_is_atsm(device->info) &&
queue->family->engine_class == INTEL_ENGINE_CLASS_COMPUTE) {
anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
pc.CommandStreamerStallEnable = true;
pc.StateCacheInvalidationEnable = true;
pc.ConstantCacheInvalidationEnable = true;
pc.UntypedDataPortCacheFlushEnable = true;
pc.TextureCacheInvalidationEnable = true;
pc.InstructionCacheInvalidateEnable = true;
pc.HDCPipelineFlushEnable = true;
genX(batch_emit_pipe_control)
(batch, device->info,
ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_STATE_CACHE_INVALIDATE_BIT |
ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT |
ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT |
ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT |
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT);
}
}
#endif
@@ -203,16 +204,15 @@ init_common_queue_state(struct anv_queue *queue, struct anv_batch *batch)
#if GFX_VER >= 12
#if GFX_VERx10 >= 125
anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
/* Wa_14016407139:
*
* "On Surface state base address modification, for 3D workloads, SW must
* always program PIPE_CONTROL either with CS Stall or PS sync stall. In
* both the cases set Render Target Cache Flush Enable".
*/
pc.RenderTargetCacheFlushEnable = true;
pc.CommandStreamerStallEnable = true;
}
/* Wa_14016407139:
*
* "On Surface state base address modification, for 3D workloads, SW must
* always program PIPE_CONTROL either with CS Stall or PS sync stall. In
* both the cases set Render Target Cache Flush Enable".
*/
genX(batch_emit_pipe_control)
(batch, device->info, ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT);
#endif
/* GEN:BUG:1607854226:
@@ -1115,9 +1115,8 @@ genX(apply_task_urb_workaround)(struct anv_cmd_buffer *cmd_buffer)
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_URB_ALLOC_TASK), zero);
/* Issue 'nullprim' to commit the state. */
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.PostSyncOperation = WriteImmediateData;
pc.Address = cmd_buffer->device->workaround_address;
}
genX(batch_emit_pipe_control_write)
(&cmd_buffer->batch, cmd_buffer->device->info,
WriteImmediateData, cmd_buffer->device->workaround_address, 0, 0);
#endif
}