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75 Commits

Author SHA1 Message Date
Caio Oliveira 67fcfed67b brw: Add FILE * parameter to dump_assembly 
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37259>
 2025-09-09 10:40:42 -07:00
Antonio Ospite ddf2aa3a4d build: avoid redefining unreachable() which is standard in C23 
In the C23 standard unreachable() is now a predefined function-like
macro in <stddef.h>

See https://android.googlesource.com/platform/bionic/+/HEAD/docs/c23.md#is-now-a-predefined-function_like-macro-in

And this causes build errors when building for C23:

-----------------------------------------------------------------------
In file included from ../src/util/log.h:30,
                 from ../src/util/log.c:30:
../src/util/macros.h:123:9: warning: "unreachable" redefined
  123 | #define unreachable(str)    \
      |         ^~~~~~~~~~~
In file included from ../src/util/macros.h:31:
/usr/lib/gcc/x86_64-linux-gnu/14/include/stddef.h:456:9: note: this is the location of the previous definition
  456 | #define unreachable() (__builtin_unreachable ())
      |         ^~~~~~~~~~~
-----------------------------------------------------------------------

So don't redefine it with the same name, but use the name UNREACHABLE()
to also signify it's a macro.

Using a different name also makes sense because the behavior of the
macro was extending the one of __builtin_unreachable() anyway, and it
also had a different signature, accepting one argument, compared to the
standard unreachable() with no arguments.

This change improves the chances of building mesa with the C23 standard,
which for instance is the default in recent AOSP versions.

All the instances of the macro, including the definition, were updated
with the following command line:

  git grep -l '[^_]unreachable(' -- "src/**" | sort | uniq | \
  while read file; \
  do \
    sed -e 's/\([^_]\)unreachable(/\1UNREACHABLE(/g' -i "$file"; \
  done && \
  sed -e 's/#undef unreachable/#undef UNREACHABLE/g' -i src/intel/isl/isl_aux_info.c

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36437>
 2025-07-31 17:49:42 +00:00
Caio Oliveira d1dd088ede brw: Allow DPAS with BF on Gfx125 
MTL doesn't support, but both ACM and ARL-H do.

Fixes: e384ccde28 ("brw: Expand EU validation for DPAS")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34506>
 2025-04-14 18:23:43 +00:00
Caio Oliveira adfab666a4 intel: Add intel_device_info::has_systolic 
Gfx125+ has systolic, with exception for MTL and some ARL
variants.  Update code and tests to use it.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34506>
 2025-04-14 18:23:43 +00:00
Caio Oliveira 9845693912 brw: Fix memory leak in EU validation tests 
Fixes: 62323a934b ("brw: Add BRW_TYPE_BF validation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34395>
 2025-04-06 06:26:03 +00:00
Caio Oliveira e384ccde28 brw: Expand EU validation for DPAS 
Allow BFloat16 types when supported and allow destination/accumulator to
match the other source types in Gfx20+.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34035>
 2025-03-25 07:38:08 +00:00
Caio Oliveira 62323a934b brw: Add BRW_TYPE_BF validation 
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33664>
 2025-03-25 05:23:37 +00:00
Caio Oliveira 9916cc1050 brw: Add BRW_TYPE_BF for bfloat16 
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33664>
 2025-03-25 05:23:37 +00:00
Caio Oliveira 228aba779f intel/brw: Rename brw_inst_* helpers to brw_eu_inst_* 
Acked-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32643>
 2024-12-30 17:16:15 +00:00
Caio Oliveira 3c3f4a1235 intel/brw: Rename brw_inst to brw_eu_inst 
Free the old name for the BRW IR instruction.

Acked-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32643>
 2024-12-30 17:16:15 +00:00
Caio Oliveira d325de316d intel/brw: Add some tests for new Xe2 register regioning restrictions 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28636>
 2024-12-14 02:15:18 +00:00
Caio Oliveira 5420c027e6 intel/brw: Add validation for ARF scalar register 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32236>
 2024-12-13 02:18:15 +00:00
Caio Oliveira cbc45ac99e intel/brw: Enable EU validation and compaction tests for PTL 
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32195>
 2024-12-04 23:03:11 +00:00
Caio Oliveira a0ea2a656f intel/brw: Enable EU validation and compaction tests for Xe2 
A few EU validation tests had to be updated to account for larger GRF,
extra supported types for 3-src instructions and the lack of AccWrEnable
in Xe2.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31299>
 2024-10-01 16:03:35 -07:00
Caio Oliveira 8b1c5425a9 intel/brw: Update DPAS validation tests for Xe2 
The main change is that in Xe2 DPAS instruction requires SIMD16.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31299>
 2024-10-01 16:03:35 -07:00
Caio Oliveira b4acc3fc42 intel/brw: Remove Gfx8- from test_eu_validate.c 
These tests only run for Gfx9+.

Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31272>
 2024-10-01 21:16:54 +00:00
Caio Oliveira 31dfb04fd3 intel/brw: Remove long register file names 
The long names were originally meant to map to the HW encoding but
nowadays the actual encoding values depend on gfx version, whether
instruction is 3src, etc.

Suggested by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30704>
 2024-08-25 22:08:14 +00:00
Kenneth Graunke df6cfb4dd0 intel/brw: Rename brw_reg_type_to_hw_type to brw_type_encode 
And similarly brw_hw_type_to_reg_type to brw_type_decode.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
 2024-04-25 11:41:48 +00:00
Kenneth Graunke 28034aac34 intel/brw: Combine a1/a16 3src type encoding functions 
Align16 is only used on Gfx9, while Align1 is used on Gfx11+.  We can
handle both encodings in the same function with a simple devinfo check,
and give that function a simple name like brw_type_encode_for_3src.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
 2024-04-25 11:41:48 +00:00
Kenneth Graunke 007d891239 intel/brw: Use newer brw_type_is_* shorter names 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
 2024-04-25 11:41:48 +00:00
Kenneth Graunke f523bfcf90 intel/brw: Reindent after shortening BRW_REGISTER_TYPE_* to BRW_TYPE_* 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
 2024-04-25 11:41:48 +00:00
Kenneth Graunke 873fcdff38 intel/brw: Stop using long BRW_REGISTER_TYPE enum names 
s/BRW_REGISTER_TYPE/BRW_TYPE/g

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
 2024-04-25 11:41:48 +00:00
Kenneth Graunke 9d8f2c4421 intel/brw: Rework BRW_REGISTER_TYPE's representation semantics 
In ancient days, we directly used the hardware register type encodings
throughout the compiler.  As more GPU generations came out, encodings
shifted, and we moved to an abstract enum that we could encode/decode
to a particular GPU's hardware encoding.  But there was no particular
meaning behind any particular value.

One downside to this approach is that we end up with switch statements
galore.  Want to know a type's size?  Switch.  Convert a unsigned type
to a signed one?  Switch.  Get a type with the same base type, but
different bit size?  Switch.  This is both inefficient and inconvenient.

In contrast, nir_alu_type takes a nicer approach - the type encoding has
certain bits representing the base type, and others encoding the size of
the type.  Switching base types or sizes is a simple matter of masking
out the relevant field and substituting a different one.

Tigerlake's encoding adopts a similar approach: two bits represent the
size as a 2-bit unsigned number n, where the bit size is (8 * 2^n).
Two more bits represent the base type.  Past encodings were a bit ad hoc
as new data types were added over time, but Gfx12 is organized (mostly).

This patch converts our brw_reg_type enum over to a new system that's
patterned after the Tigerlake style (for easy conversion) while
deviating in a few ways that make our vector immediate type size
handling simpler.  Should we add additional base types, we're likely
to continue deviating.  Still, converting is much simpler.

Type size calculations (which are performed all the time) are now a
simple mask and shift, instead of a switch.

We also adopt the name BRW_TYPE_* instead of BRW_REGISTER_TYPE_* because
it's much shorter and easier to type.  Similarly, we create new helper
functions named brw_type_* for working with these types, with a cleaner
naming convention.  Legacy names still exist but will we dropped over
the next few patches as pieces get cleaned up.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
 2024-04-25 11:41:48 +00:00
Kenneth Graunke c45e235df5 intel/brw: Drop NF type support 
Icelake removed the PLN instruction for interpolating fragment shader
inputs, instead adding a special "Native Float" (NF) data type which
was a 66-bit floating point data type that could only be used with the
accumulator.  On Tigerlake, they dropped NF support in favor of just
doing the interpolation with MAD instructions.

We stopped using NF years ago (commit 9ea90aae1e),
instead just using the fs_visitor::lower_linterp() pass to emit MADs.

Since this existed only for a short time, and had very limited utility,
we drop it from the compiler.  One downside is that we can no longer
disassemble Icelake shaders containing NF types properly, but I doubt
anyone really minds.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
 2024-04-25 11:41:48 +00:00
Caio Oliveira 8f3c52c1da intel/brw: Remove MRF type 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:39 +00:00
Caio Oliveira 8c3165f0ff intel/brw: Remove EU validation tests for Gfx8- 
Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27768>
 2024-02-24 02:10:56 +00:00
Caio Oliveira 468a0ffe9c intel/compiler: Include brw_disasm_info.h where its used 
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27579>
 2024-02-15 09:26:46 +00:00
Ian Romanick eb1f19d7bf intel/compiler: Validation for DPAS instructions 
v2: s/regiser/register/g in messages. Noticed by Caio. Add more context
to the sub-byte precision error message. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994>
 2023-12-29 20:27:15 -08:00
Sviatoslav Peleshko 8361cd4c4c intel/eu/validate: Validate "packed word exception" stricter 
Fixes: 75b7f5a2 ("i965: Validate "Region Alignment Rules"")
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25378>
 2023-10-05 01:41:42 +00:00
Ian Romanick 78dd15d8e8 intel/eu/validate: Add some validation of ADD3 
v2: Remove spurious ALIGN_1 checks. Suggested by Matt.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23262>
 2023-06-06 06:10:53 +00:00
Ian Romanick 1c4c76032b intel/eu/validate: Add Gfx12.5 
This required updating the expected results in a number of test. The
vast majority of these are cases where Gfx12.5 platforms don't allow
mixing F and HF sources.

In all honesty... I just updated the half_float_conversion expected
results until the test passed.

The next commit will add changes specific to Gfx12.5.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23262>
 2023-06-06 06:10:53 +00:00
Ian Romanick a3cfec0690 intel/eu/validate: Use a single macro define half_float_conversion cases 
This is what other tests do. The next commit will add a third set of
possible results (for Gfx12.5+), and the multiple macro method does not
scale.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23262>
 2023-06-06 06:10:53 +00:00
Ian Romanick ee2a299661 intel/eu/validate: Validate integer multiplication source size restrictions 
v2: Expect correct result on BDW in test_eu.

v3: Fix SNB type-size check. Noticed by Marcin.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>
 2022-11-09 21:34:26 +00:00
Yonggang Luo 4bfde7954e intel/compiler: Fixes [-Wdeprecated-declarations] in test_eu_validate.cpp 
Warning message:
../src/intel/compiler/test_eu_validate.cpp:96:1: warning: 'InstantiateTestCase_P_IsDeprecated' is deprecated: INSTANTIATE_TEST_CASE_P is deprecated, please use INSTANTIATE_TEST_SUITE_P [-Wdeprecated-declarations]

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18203>
 2022-08-23 15:19:16 +00:00
Kenneth Graunke 72e9843991 intel/compiler: Introduce a new brw_isa_info structure 
This structure will contain the opcode mapping tables in the next
commit.  For now, this is the mechanical change to plumb it into all
the necessary places, and it continues simply holding devinfo.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
 2022-06-30 23:46:35 +00:00
Lionel Landwerlin 361b3fee3c intel: move away from booleans to identify platforms 
v2: Drop changes around GFX_VERx10 == 75 (Luis)

v3: Replace
   (GFX_VERx10 < 75 && devinfo->platform != INTEL_PLATFORM_BYT)
   by
   (devinfo->platform == INTEL_PLATFORM_IVB)
   Replace
   (devinfo->ver >= 5 || devinfo->platform == INTEL_PLATFORM_G4X)
   by
   (devinfo->verx10 >= 45)
   Replace
   (devinfo->platform != INTEL_PLATFORM_G4X)
   by
   (devinfo->verx10 != 45)

v4: Fix crocus typo

v5: Rebase

v6: Add GFX3, ILK & I965 platforms (Jordan)
    Move ifdef to code expressions (Jordan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12981>
 2021-11-08 16:48:06 +00:00
Marcin Ślusarz 3340d5ee02 intel: simplify is_haswell checks, part 1 
Generated with:

files=`git grep is_haswell | cut -d: -f1 | sort | uniq`
for file in $files; do
        cat $file | \
                sed "s/devinfo->ver <= 7 && !devinfo->is_haswell/devinfo->verx10 <= 70/g" | \
                sed "s/devinfo->ver >= 8 || devinfo->is_haswell/devinfo->verx10 >= 75/g" | \
                sed "s/devinfo->is_haswell || devinfo->ver >= 8/devinfo->verx10 >= 75/g" | \
                sed "s/devinfo.is_haswell || devinfo.ver >= 8/devinfo.verx10 >= 75/g" | \
                sed "s/devinfo->ver > 7 || devinfo->is_haswell/devinfo->verx10 >= 75/g" | \
                sed "s/devinfo->ver == 7 && !devinfo->is_haswell/devinfo->verx10 == 70/g" | \
                sed "s/devinfo.ver == 7 && !devinfo.is_haswell/devinfo.verx10 == 70/g" | \
                sed "s/devinfo->ver < 8 && !devinfo->is_haswell/devinfo->verx10 <= 70/g" | \
                sed "s/device->info.ver == 7 && !device->info.is_haswell/device->info.verx10 == 70/g" \
                > tmpXXX
        mv tmpXXX $file
done

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10810>
 2021-05-17 09:46:45 +00:00
Anuj Phogat ea13901354 intel: Rename gen keyword in test_eu_validate.cpp 
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
 2021-04-20 20:06:34 +00:00
Anuj Phogat 726d9696dd intel: Rename gen_get_device prefix to intel_get_device 
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen_get_device" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_get_device/intel_get_device/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
 2021-04-20 20:06:34 +00:00
Anuj Phogat 61e8636557 intel: Rename gen_device prefix to intel_device 
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen_device" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_device/intel_device/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
 2021-04-20 20:06:33 +00:00
Anuj Phogat 1d296484b4 intel: Rename Genx keyword to Gfxx 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "Gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/Gen\([[:digit:]]\+\)/Gfx\1/g"

Exclude changes in src/intel/perf/oa-*.xml:
find src/intel/perf -type f \( -name "*.xml" \) | xargs sed -ie "s/Gfx/Gen/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat b75f095bc7 intel: Rename genx keyword to gfxx in source files 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/gen\([[:digit:]]\+\)/gfx\1/g"

Exclude pack.h and xml changes in this patch:
grep -E "gfx[[:digit:]]+_pack\.h" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+_pack\.h\)/gen\1/g"
grep -E "gfx[[:digit:]]+\.xml" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+\.xml\)/gen\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat abe9a71a09 intel: Rename gen field in gen_device_info struct to ver 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "info\)*(.|->)gen" -rIl $SEARCH_PATH | xargs sed -ie "s/info\()*\)\(\.\|->\)gen/info\1\2ver/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Ian Romanick 262ca98b3a intel/compiler: Remove Gen10-specific code 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6899>
 2020-10-15 09:29:53 -07:00
Danylo Piliaiev bc4a127d6e intel/disasm: Label support in shader disassembly for UIP/JIP 
Shader instructions which use UIP/JIP now get formatted with a label
in addition with immediate value, labels have "LABEL%d" format.

v2: - Consider brw_jump_scale when calculating label's offset

From: "Lonnberg, Toni" <toni.lonnberg@intel.com>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245>
 2020-09-02 10:33:29 +00:00
Francisco Jerez 486f3b04a5 intel/ir: Pass block cycle count information explicitly to disassembler. 
So we can eventually remove the cycle count estimates from the CFG
data structure and consolidate performance information in the
brw::performance object.

It would be cleaner to pass the brw::performance object directly to
the disassembler but that isn't straightforward since the disassembler
is built as a plain C file unlike the rest of the compiler back-end.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2020-04-28 23:01:27 -07:00
Matt Turner 4413537c80 util: Remove tmp argument from BITSET_FOREACH_SET macro 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3499>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3499>
 2020-01-23 01:52:43 +00:00
Matt Turner 72cf63cfc6 intel/compiler: Add unit tests for new EU validation checks 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
 2020-01-22 00:19:21 +00:00
Matt Turner 49c21802cb intel/compiler: Split has_64bit_types into float/int 
Gen7 has 64-bit floats but not 64-bit ints.

Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
 2020-01-22 00:19:20 +00:00
Matt Turner c69f3ece61 intel/compiler: Use ARRAY_SIZE() 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>
 2020-01-22 00:19:20 +00:00