AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/brw: Use newer brw_type_is_* shorter names

Browse Source 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
This commit is contained in:
Kenneth Graunke
2024-04-20 23:19:43 -07:00
committed by Marge Bot
parent f523bfcf90
commit 007d891239
16 changed files with 59 additions and 77 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/brw_eu_emit.c
+2 -2
View File
@@ -586,7 +586,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
brw_inst_set_3src_a1_dst_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest) / 8);
brw_inst_set_3src_a1_dst_hstride(devinfo, inst, BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1);
if (brw_reg_type_is_floating_point(dest.type)) {
if (brw_type_is_float(dest.type)) {
brw_inst_set_3src_a1_exec_type(devinfo, inst,
BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT);
} else {
@@ -755,7 +755,7 @@ brw_dpas_three_src(struct brw_codegen *p, enum gfx12_systolic_depth opcode,
brw_inst_set_dpas_3src_dst_reg_nr(devinfo, inst, phys_nr(devinfo, dest));
brw_inst_set_dpas_3src_dst_subreg_nr(devinfo, inst, phys_subnr(devinfo, dest));
if (brw_reg_type_is_floating_point(dest.type)) {
if (brw_type_is_float(dest.type)) {
brw_inst_set_dpas_3src_exec_type(devinfo, inst,
BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT);
} else {
src/intel/compiler/brw_eu_validate.c
+13 -13
View File
@@ -896,9 +896,9 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
*/
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
if ((dst_type == BRW_TYPE_HF &&
(brw_reg_type_is_integer(src0_type) ||
(num_sources > 1 && brw_reg_type_is_integer(src1_type)))) ||
(brw_reg_type_is_integer(dst_type) &&
(brw_type_is_int(src0_type) ||
(num_sources > 1 && brw_type_is_int(src1_type)))) ||
(brw_type_is_int(dst_type) &&
(src0_type == BRW_TYPE_HF ||
(num_sources > 1 && src1_type == BRW_TYPE_HF)))) {
ERROR_IF(dst_stride * dst_type_size != 4,
@@ -1732,7 +1732,7 @@ special_requirements_for_handling_double_precision_data_types(
* used."
*/
if (devinfo->verx10 >= 125 &&
(brw_reg_type_is_floating_point(dst_type) ||
(brw_type_is_float(dst_type) ||
is_double_precision)) {
ERROR_IF(!is_scalar_region &&
BRW_ADDRESS_REGISTER_INDIRECT_REGISTER != address_mode &&
@@ -1758,7 +1758,7 @@ special_requirements_for_handling_double_precision_data_types(
* Quad-Word data must not be used."
*/
if (devinfo->verx10 >= 125 &&
(brw_reg_type_is_floating_point(type) || type_sz(type) == 8)) {
(brw_type_is_float(type) || type_sz(type) == 8)) {
ERROR_IF(address_mode == BRW_ADDRESS_REGISTER_INDIRECT_REGISTER &&
vstride == BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL,
"Vx1 and VxH indirect addressing for Float, Half-Float, "
@@ -1829,7 +1829,7 @@ instruction_restrictions(const struct brw_isa_info *isa,
!(brw_inst_src1_negate(devinfo, inst) ||
brw_inst_src1_abs(devinfo, inst));
ERROR_IF(!brw_reg_type_is_floating_point(exec_type) &&
ERROR_IF(!brw_type_is_float(exec_type) &&
type_sz(exec_type) == 4 && !(src0_valid && src1_valid),
"When multiplying a DW and any lower precision integer, source "
"modifier is not supported.");
@@ -1860,7 +1860,7 @@ instruction_restrictions(const struct brw_isa_info *isa,
* Ivy Bridge, Haswell, Skylake, and Ice Lake PRMs contain the same
* text.
*/
ERROR_IF(brw_reg_type_is_integer(src1_type) &&
ERROR_IF(brw_type_is_int(src1_type) &&
type_sz(src0_type) < 4 && type_sz(src1_type) == 4,
"When multiplying a DW and any lower precision integer, the "
"DW operand must be src0.");
@@ -1873,9 +1873,9 @@ instruction_restrictions(const struct brw_isa_info *isa,
* The Skylake and Ice Lake PRMs contain the same text.
*/
ERROR_IF((src0_is_acc(devinfo, inst) &&
brw_reg_type_is_integer(src0_type)) ||
brw_type_is_int(src0_type)) ||
(src1_is_acc(devinfo, inst) &&
brw_reg_type_is_integer(src1_type)),
brw_type_is_int(src1_type)),
"Integer source operands cannot be accumulators.");
/* Page 935 (page 951 of the PDF) of the Ice Lake PRM volume 2a says:
@@ -2253,10 +2253,10 @@ instruction_restrictions(const struct brw_isa_info *isa,
src2_type != BRW_TYPE_UB,
"DPAS src2 base type must be B or UB.");
if (brw_reg_type_is_unsigned_integer(dst_type)) {
ERROR_IF(!brw_reg_type_is_unsigned_integer(src0_type) ||
!brw_reg_type_is_unsigned_integer(src1_type) ||
!brw_reg_type_is_unsigned_integer(src2_type),
if (brw_type_is_uint(dst_type)) {
ERROR_IF(!brw_type_is_uint(src0_type) ||
!brw_type_is_uint(src1_type) ||
!brw_type_is_uint(src2_type),
"If any source datatype is signed, destination datatype "
"must be signed.");
}
src/intel/compiler/brw_fs.cpp
+2 -2
View File
@@ -440,7 +440,7 @@ fs_inst::can_do_source_mods(const struct intel_device_info *devinfo) const
MIN2(type_sz(src[1].type), type_sz(src[2].type)) :
MIN2(type_sz(src[0].type), type_sz(src[1].type));
if (brw_reg_type_is_integer(exec_type) &&
if (brw_type_is_int(exec_type) &&
type_sz(exec_type) >= 4 &&
type_sz(exec_type) != min_type_sz)
return false;
@@ -521,7 +521,7 @@ fs_inst::can_do_cmod() const
* equality with a 32-bit value. See piglit fs-op-neg-uvec4.
*/
for (unsigned i = 0; i < sources; i++) {
if (brw_reg_type_is_unsigned_integer(src[i].type) && src[i].negate)
if (brw_type_is_uint(src[i].type) && src[i].negate)
return false;
}
src/intel/compiler/brw_fs_cmod_propagation.cpp
+13 -13
View File
@@ -124,8 +124,8 @@ cmod_propagate_cmp_to_add(const intel_device_info *devinfo, bblock_t *block,
: inst->conditional_mod;
if (scan_inst->saturate &&
(brw_reg_type_is_floating_point(scan_inst->dst.type) ||
brw_reg_type_is_unsigned_integer(scan_inst->dst.type)) &&
(brw_type_is_float(scan_inst->dst.type) ||
brw_type_is_uint(scan_inst->dst.type)) &&
(cond != BRW_CONDITIONAL_G &&
cond != BRW_CONDITIONAL_LE))
goto not_match;
@@ -270,7 +270,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
* less than zero, so the flags get set differently than for (a < b).
*/
if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero()) {
if (brw_reg_type_is_floating_point(inst->src[0].type) &&
if (brw_type_is_float(inst->src[0].type) &&
cmod_propagate_cmp_to_add(devinfo, block, inst))
progress = true;
@@ -310,7 +310,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
/* CMP's result is the same regardless of dest type. */
if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
scan_inst->opcode == BRW_OPCODE_CMP &&
brw_reg_type_is_integer(inst->dst.type)) {
brw_type_is_int(inst->dst.type)) {
inst->remove(block, true);
progress = true;
break;
@@ -323,7 +323,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
break;
if (inst->opcode == BRW_OPCODE_MOV) {
if (brw_reg_type_is_floating_point(scan_inst->dst.type)) {
if (brw_type_is_float(scan_inst->dst.type)) {
/* If the destination type of scan_inst is floating-point,
* then:
*
@@ -338,7 +338,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
if (scan_inst->dst.type != inst->src[0].type)
break;
if (!brw_reg_type_is_floating_point(inst->dst.type))
if (!brw_type_is_float(inst->dst.type))
break;
if (type_sz(scan_inst->dst.type) > type_sz(inst->dst.type))
@@ -359,18 +359,18 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
* (of any size) or integer with a size at least as large
* as the destination of inst and the same signedness.
*/
if (!brw_reg_type_is_integer(inst->src[0].type) ||
if (!brw_type_is_int(inst->src[0].type) ||
type_sz(scan_inst->dst.type) != type_sz(inst->src[0].type))
break;
if (brw_reg_type_is_integer(inst->dst.type)) {
if (brw_type_is_int(inst->dst.type)) {
if (type_sz(inst->dst.type) < type_sz(scan_inst->dst.type))
break;
if (inst->conditional_mod != BRW_CONDITIONAL_Z &&
inst->conditional_mod != BRW_CONDITIONAL_NZ &&
brw_reg_type_is_unsigned_integer(inst->dst.type) !=
brw_reg_type_is_unsigned_integer(scan_inst->dst.type))
brw_type_is_uint(inst->dst.type) !=
brw_type_is_uint(scan_inst->dst.type))
break;
}
}
@@ -391,8 +391,8 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
if (type_sz(scan_inst->dst.type) != type_sz(inst->dst.type))
break;
if (brw_reg_type_is_floating_point(scan_inst->dst.type) !=
brw_reg_type_is_floating_point(inst->dst.type))
if (brw_type_is_float(scan_inst->dst.type) !=
brw_type_is_float(inst->dst.type))
break;
}
}
@@ -490,7 +490,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
*
* We just disallow cmod propagation on all integer multiplies.
*/
if (!brw_reg_type_is_floating_point(scan_inst->dst.type) &&
if (!brw_type_is_float(scan_inst->dst.type) &&
scan_inst->opcode == BRW_OPCODE_MUL)
break;
src/intel/compiler/brw_fs_combine_constants.cpp
+1 -1
View File
@@ -1093,7 +1093,7 @@ add_candidate_immediate(struct table *table, fs_inst *inst, unsigned ip,
v->no_negations = !inst->can_do_source_mods(devinfo) ||
((inst->opcode == BRW_OPCODE_SHR ||
inst->opcode == BRW_OPCODE_ASR) &&
brw_reg_type_is_unsigned_integer(inst->src[i].type));
brw_type_is_uint(inst->src[i].type));
switch (inst->src[i].type) {
case BRW_TYPE_DF:
src/intel/compiler/brw_fs_lower_dpas.cpp
+1 -1
View File
@@ -281,7 +281,7 @@ brw_fs_lower_dpas(fs_visitor &v)
const fs_builder bld = fs_builder(&v, block, inst).group(8, 0).exec_all();
if (brw_reg_type_is_floating_point(inst->dst.type)) {
if (brw_type_is_float(inst->dst.type)) {
f16_using_mac(bld, inst);
} else {
if (v.devinfo->ver >= 12) {
src/intel/compiler/brw_fs_lower_regioning.cpp
+3 -3
View File
@@ -220,7 +220,7 @@ namespace {
required_exec_type(const intel_device_info *devinfo, const fs_inst *inst)
{
const brw_reg_type t = get_exec_type(inst);
const bool has_64bit = brw_reg_type_is_floating_point(t) ?
const bool has_64bit = brw_type_is_float(t) ?
devinfo->has_64bit_float : devinfo->has_64bit_int;
switch (inst->opcode) {
@@ -454,7 +454,7 @@ namespace brw {
assert(inst->components_read(i) == 1);
assert(v->devinfo->has_integer_dword_mul ||
inst->opcode != BRW_OPCODE_MUL ||
brw_reg_type_is_floating_point(get_exec_type(inst)) ||
brw_type_is_float(get_exec_type(inst)) ||
MIN2(type_sz(inst->src[0].type), type_sz(inst->src[1].type)) >= 4 ||
type_sz(inst->src[i].type) == get_exec_type_size(inst));
@@ -595,7 +595,7 @@ namespace {
* accumulator.
*/
assert(inst->opcode != BRW_OPCODE_MUL || !inst->dst.is_accumulator() ||
brw_reg_type_is_floating_point(inst->dst.type));
brw_type_is_float(inst->dst.type));
const fs_builder ibld(v, block, inst);
const unsigned stride = required_dst_byte_stride(inst) /
src/intel/compiler/brw_fs_opt_algebraic.cpp
+2 -2
View File
@@ -110,7 +110,7 @@ brw_fs_opt_algebraic(fs_visitor &s)
if (inst->src[0].file != IMM && inst->src[1].file != IMM)
continue;
if (brw_reg_type_is_floating_point(inst->src[1].type))
if (brw_type_is_float(inst->src[1].type))
break;
/* From the BDW PRM, Vol 2a, "mul - Multiply":
@@ -179,7 +179,7 @@ brw_fs_opt_algebraic(fs_visitor &s)
if (inst->src[1].file != IMM)
continue;
if (brw_reg_type_is_integer(inst->src[1].type) &&
if (brw_type_is_int(inst->src[1].type) &&
inst->src[1].is_zero()) {
inst->opcode = BRW_OPCODE_MOV;
inst->sources = 1;
src/intel/compiler/brw_fs_scoreboard.cpp
+4 -4
View File
@@ -85,7 +85,7 @@ namespace {
if (inst->src[i].file != BAD_FILE &&
!inst->is_control_source(i)) {
const brw_reg_type t = inst->src[i].type;
has_int_src |= !brw_reg_type_is_floating_point(t);
has_int_src |= !brw_type_is_float(t);
has_long_src |= type_sz(t) >= 8;
}
}
@@ -118,7 +118,7 @@ namespace {
inferred_exec_pipe(const struct intel_device_info *devinfo, const fs_inst *inst)
{
const brw_reg_type t = get_exec_type(inst);
const bool is_dword_multiply = !brw_reg_type_is_floating_point(t) &&
const bool is_dword_multiply = !brw_type_is_float(t) &&
((inst->opcode == BRW_OPCODE_MUL &&
MIN2(type_sz(inst->src[0].type), type_sz(inst->src[1].type)) >= 4) ||
(inst->opcode == BRW_OPCODE_MAD &&
@@ -137,7 +137,7 @@ namespace {
else if (inst->opcode == FS_OPCODE_PACK_HALF_2x16_SPLIT)
return TGL_PIPE_FLOAT;
else if (devinfo->ver >= 20 && type_sz(inst->dst.type) >= 8 &&
brw_reg_type_is_floating_point(inst->dst.type)) {
brw_type_is_float(inst->dst.type)) {
assert(devinfo->has_64bit_float);
return TGL_PIPE_LONG;
} else if (devinfo->ver < 20 &&
@@ -146,7 +146,7 @@ namespace {
assert(devinfo->has_64bit_float || devinfo->has_64bit_int ||
devinfo->has_integer_dword_mul);
return TGL_PIPE_LONG;
} else if (brw_reg_type_is_floating_point(inst->dst.type))
} else if (brw_type_is_float(inst->dst.type))
return TGL_PIPE_FLOAT;
else
return TGL_PIPE_INT;
src/intel/compiler/brw_fs_validate.cpp
+6 -6
View File
@@ -110,13 +110,13 @@ brw_fs_validate(const fs_visitor &s)
if (inst->is_3src(s.compiler)) {
const unsigned integer_sources =
brw_reg_type_is_integer(inst->src[0].type) +
brw_reg_type_is_integer(inst->src[1].type) +
brw_reg_type_is_integer(inst->src[2].type);
brw_type_is_int(inst->src[0].type) +
brw_type_is_int(inst->src[1].type) +
brw_type_is_int(inst->src[2].type);
const unsigned float_sources =
brw_reg_type_is_floating_point(inst->src[0].type) +
brw_reg_type_is_floating_point(inst->src[1].type) +
brw_reg_type_is_floating_point(inst->src[2].type);
brw_type_is_float(inst->src[0].type) +
brw_type_is_float(inst->src[1].type) +
brw_type_is_float(inst->src[2].type);
fsv_assert((integer_sources == 3 && float_sources == 0) ||
(integer_sources == 0 && float_sources == 3));
src/intel/compiler/brw_inst.h
+2 -2
View File
@@ -450,7 +450,7 @@ brw_inst_set_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
UNUSED enum gfx10_align1_3src_exec_type exec_type = \
(enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
inst); \
if (brw_reg_type_is_floating_point(type)) { \
if (brw_type_is_float(type)) { \
assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
} else { \
assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
@@ -560,7 +560,7 @@ brw_inst_set_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \
UNUSED enum gfx10_align1_3src_exec_type exec_type = \
(enum gfx10_align1_3src_exec_type) brw_inst_dpas_3src_exec_type(devinfo,\
inst); \
if (brw_reg_type_is_floating_point(type)) { \
if (brw_type_is_float(type)) { \
assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
} else { \
assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
src/intel/compiler/brw_ir_fs.h
+5 -5
View File
@@ -660,7 +660,7 @@ get_exec_type(const fs_inst *inst)
if (type_sz(t) > type_sz(exec_type))
exec_type = t;
else if (type_sz(t) == type_sz(exec_type) &&
brw_reg_type_is_floating_point(t))
brw_type_is_float(t))
exec_type = t;
}
}
@@ -781,7 +781,7 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo,
* simulator suggest that only 32x32-bit integer multiplication is
* restricted.
*/
const bool is_dword_multiply = !brw_reg_type_is_floating_point(exec_type) &&
const bool is_dword_multiply = !brw_type_is_float(exec_type) &&
((inst->opcode == BRW_OPCODE_MUL &&
MIN2(type_sz(inst->src[0].type), type_sz(inst->src[1].type)) >= 4) ||
(inst->opcode == BRW_OPCODE_MAD &&
@@ -791,7 +791,7 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo,
(type_sz(exec_type) == 4 && is_dword_multiply))
return intel_device_info_is_9lp(devinfo) || devinfo->verx10 >= 125;
else if (brw_reg_type_is_floating_point(dst_type))
else if (brw_type_is_float(dst_type))
return devinfo->verx10 >= 125;
else
@@ -817,10 +817,10 @@ has_subdword_integer_region_restriction(const intel_device_info *devinfo,
const fs_reg *srcs, unsigned num_srcs)
{
if (devinfo->ver >= 20 &&
brw_reg_type_is_integer(inst->dst.type) &&
brw_type_is_int(inst->dst.type) &&
MAX2(byte_stride(inst->dst), type_sz(inst->dst.type)) < 4) {
for (unsigned i = 0; i < num_srcs; i++) {
if (brw_reg_type_is_integer(srcs[i].type) &&
if (brw_type_is_int(srcs[i].type) &&
type_sz(srcs[i].type) < 4 && byte_stride(srcs[i]) >= 4)
return true;
}
src/intel/compiler/brw_ir_performance.cpp
+2 -2
View File
@@ -142,7 +142,7 @@ namespace {
* Treat it as double-precision.
*/
if ((inst->opcode == BRW_OPCODE_MUL || inst->opcode == BRW_OPCODE_MAD) &&
!brw_reg_type_is_floating_point(tx) && type_sz(tx) == 4 &&
!brw_type_is_float(tx) && type_sz(tx) == 4 &&
type_sz(inst->src[0].type) == type_sz(inst->src[1].type))
tx = brw_int_type(8, tx == BRW_TYPE_D);
@@ -855,7 +855,7 @@ namespace {
assert(inst->reads_accumulator_implicitly() ||
inst->writes_accumulator_implicitly(devinfo));
const unsigned offset = (inst->group + i) * type_sz(tx) *
(brw_reg_type_is_floating_point(tx) ? 1 : 2);
(brw_type_is_float(tx) ? 1 : 2);
return offset / (reg_unit(devinfo) * REG_SIZE) % 2;
}
src/intel/compiler/brw_reg_type.h
-18
View File
@@ -153,24 +153,6 @@ brw_type_with_size(enum brw_reg_type ref_type, unsigned bit_size)
/* -------------------------------------------------------------- */
static inline bool
brw_reg_type_is_floating_point(enum brw_reg_type type)
{
return brw_type_is_float(type);
}
static inline bool
brw_reg_type_is_integer(enum brw_reg_type type)
{
return brw_type_is_int(type);
}
static inline bool
brw_reg_type_is_unsigned_integer(enum brw_reg_type tp)
{
return brw_type_is_uint(tp);
}
/*
* Returns a type based on a reference_type (word, float, half-float) and a
* given bit_size.
src/intel/compiler/brw_shader.cpp
+1 -1
View File
@@ -301,7 +301,7 @@ fs_inst::is_commutative() const
/* Integer multiplication of dword and word sources is not actually
* commutative. The DW source must be first.
*/
return !brw_reg_type_is_integer(src[0].type) ||
return !brw_type_is_int(src[0].type) ||
type_sz(src[0].type) == type_sz(src[1].type);
case BRW_OPCODE_SEL:
src/intel/compiler/test_eu_validate.cpp
+2 -2
View File
@@ -374,7 +374,7 @@ TEST_P(validation_test, invalid_type_encoding_3src_a16)
}
struct brw_reg g = retype(g0, test_case[i].type);
if (!brw_reg_type_is_integer(test_case[i].type)) {
if (!brw_type_is_int(test_case[i].type)) {
brw_MAD(p, g, g, g, g);
} else {
brw_BFE(p, g, g, g, g);
@@ -465,7 +465,7 @@ TEST_P(validation_test, invalid_type_encoding_3src_a1)
}
struct brw_reg g = retype(g0, test_case[i].type);
if (!brw_reg_type_is_integer(test_case[i].type)) {
if (!brw_type_is_int(test_case[i].type)) {
brw_MAD(p, g, g, g, g);
} else {
brw_BFE(p, g, g, g, g);