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intel/brw: Drop NF type support

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Icelake removed the PLN instruction for interpolating fragment shader
inputs, instead adding a special "Native Float" (NF) data type which
was a 66-bit floating point data type that could only be used with the
accumulator.  On Tigerlake, they dropped NF support in favor of just
doing the interpolation with MAD instructions.

We stopped using NF years ago (commit 9ea90aae1e),
instead just using the fs_visitor::lower_linterp() pass to emit MADs.

Since this existed only for a short time, and had very limited utility,
we drop it from the compiler.  One downside is that we can no longer
disassemble Icelake shaders containing NF types properly, but I doubt
anyone really minds.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
This commit is contained in:
Kenneth Graunke
2023-07-14 01:06:46 -07:00
committed by Marge Bot
parent 1c6f863fc7
commit c45e235df5
12 changed files with 3 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/brw_disasm.c
-4
View File
@@ -1229,9 +1229,6 @@ src0_3src(FILE *file, const struct intel_device_info *devinfo,
} else if (brw_inst_3src_a1_src0_reg_file(devinfo, inst) ==
BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
_file = BRW_GENERAL_REGISTER_FILE;
} else if (brw_inst_3src_a1_src0_type(devinfo, inst) ==
BRW_REGISTER_TYPE_NF) {
_file = BRW_ARCHITECTURE_REGISTER_FILE;
} else {
_file = BRW_IMMEDIATE_VALUE;
uint16_t imm_val = brw_inst_3src_a1_src0_imm(devinfo, inst);
@@ -1587,7 +1584,6 @@ imm(FILE *file, const struct brw_isa_info *isa, enum brw_reg_type type,
format(file, "/* %-gHF */",
_mesa_half_to_float((uint16_t) brw_inst_imm_ud(devinfo, inst)));
break;
case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
format(file, "*** invalid immediate type %d ", type);
src/intel/compiler/brw_eu_compact.c
-2
View File
@@ -1507,7 +1507,6 @@ compact_immediate(const struct intel_device_info *devinfo,
if (((short)imm >> 11) == 0 || ((short)imm >> 11) == -1)
return imm & 0xfff;
break;
case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_Q:
case BRW_REGISTER_TYPE_UQ:
@@ -1550,7 +1549,6 @@ uncompact_immediate(const struct intel_device_info *devinfo,
/* Extend the 12th bit into the high 4 bits and replicate */
return ((int)(compact_imm << 20) >> 4) |
((unsigned short)((short)(compact_imm << 4) >> 4));
case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_Q:
case BRW_REGISTER_TYPE_UQ:
src/intel/compiler/brw_eu_emit.c
+2 -8
View File
@@ -607,11 +607,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
brw_inst_set_3src_a1_src0_hstride(devinfo, inst,
to_3src_align1_hstride(src0.hstride));
brw_inst_set_3src_a1_src0_subreg_nr(devinfo, inst, phys_subnr(devinfo, src0));
if (src0.type == BRW_REGISTER_TYPE_NF) {
brw_inst_set_3src_src0_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR);
} else {
brw_inst_set_3src_src0_reg_nr(devinfo, inst, phys_nr(devinfo, src0));
}
brw_inst_set_3src_src0_reg_nr(devinfo, inst, phys_nr(devinfo, src0));
brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs);
brw_inst_set_3src_src0_negate(devinfo, inst, src0.negate);
}
@@ -642,9 +638,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
}
assert(src0.file == BRW_GENERAL_REGISTER_FILE ||
src0.file == BRW_IMMEDIATE_VALUE ||
(src0.file == BRW_ARCHITECTURE_REGISTER_FILE &&
src0.type == BRW_REGISTER_TYPE_NF));
src0.file == BRW_IMMEDIATE_VALUE);
assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
(src1.file == BRW_ARCHITECTURE_REGISTER_FILE &&
src1.nr == BRW_ARF_ACCUMULATOR));
src/intel/compiler/brw_eu_validate.c
-5
View File
@@ -445,7 +445,6 @@ static enum brw_reg_type
execution_type_for_type(enum brw_reg_type type)
{
switch (type) {
case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_F:
case BRW_REGISTER_TYPE_HF:
@@ -506,10 +505,6 @@ execution_type(const struct brw_isa_info *isa, const brw_inst *inst)
if (src0_exec_type == src1_exec_type)
return src0_exec_type;
if (src0_exec_type == BRW_REGISTER_TYPE_NF ||
src1_exec_type == BRW_REGISTER_TYPE_NF)
return BRW_REGISTER_TYPE_NF;
if (src0_exec_type == BRW_REGISTER_TYPE_Q ||
src1_exec_type == BRW_REGISTER_TYPE_Q)
return BRW_REGISTER_TYPE_Q;
src/intel/compiler/brw_fs_combine_constants.cpp
-1
View File
@@ -1097,7 +1097,6 @@ add_candidate_immediate(struct table *table, fs_inst *inst, unsigned ip,
switch (inst->src[i].type) {
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_F:
case BRW_REGISTER_TYPE_HF:
v->type = float_only;
src/intel/compiler/brw_gram.y
+1 -2
View File
@@ -366,7 +366,7 @@ add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type t
%token <integer> TYPE_Q TYPE_UQ
%token <integer> TYPE_V TYPE_UV
%token <integer> TYPE_F TYPE_HF
%token <integer> TYPE_DF TYPE_NF
%token <integer> TYPE_DF
%token <integer> TYPE_VF
/* label */
@@ -1875,7 +1875,6 @@ reg_type:
| TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; }
| TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; }
| TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; }
| TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; }
;
imm_type:
src/intel/compiler/brw_lex.l
-1
View File
@@ -303,7 +303,6 @@ switch { return SWITCH; }
:?DF { return TYPE_DF; }
:?F { return TYPE_F; }
:?HF { return TYPE_HF; }
:?NF { return TYPE_NF; }
:?Q { return TYPE_Q; }
:?UB { return TYPE_UB; }
:?UD { return TYPE_UD; }
src/intel/compiler/brw_reg.h
-2
View File
@@ -265,7 +265,6 @@ brw_regs_negative_equal(const struct brw_reg *a, const struct brw_reg *b)
return false;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
case BRW_REGISTER_TYPE_NF:
default:
unreachable("not reached");
}
@@ -292,7 +291,6 @@ type_sz(unsigned type)
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_NF:
return 8;
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_D:
src/intel/compiler/brw_reg_type.c
-6
View File
@@ -52,7 +52,6 @@ enum hw_reg_type {
GFX11_HW_REG_TYPE_HF = 8,
GFX11_HW_REG_TYPE_F = 9,
GFX11_HW_REG_TYPE_DF = 10,
GFX11_HW_REG_TYPE_NF = 11,
};
enum hw_imm_type {
@@ -112,7 +111,6 @@ static const struct hw_type {
}, gfx11_hw_type[] = {
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
[BRW_REGISTER_TYPE_NF] = { GFX11_HW_REG_TYPE_NF, INVALID },
[BRW_REGISTER_TYPE_F] = { GFX11_HW_REG_TYPE_F, GFX11_HW_IMM_TYPE_F },
[BRW_REGISTER_TYPE_HF] = { GFX11_HW_REG_TYPE_HF, GFX11_HW_IMM_TYPE_HF },
[BRW_REGISTER_TYPE_VF] = { INVALID, GFX11_HW_IMM_TYPE_VF },
@@ -180,7 +178,6 @@ enum hw_3src_reg_type {
GFX10_ALIGN1_3SRC_REG_TYPE_HF = 0b000,
GFX10_ALIGN1_3SRC_REG_TYPE_F = 0b001,
GFX10_ALIGN1_3SRC_REG_TYPE_DF = 0b010,
GFX11_ALIGN1_3SRC_REG_TYPE_NF = 0b011,
/** @} */
/** When ExecutionDatatype is 0: @{ */
@@ -208,7 +205,6 @@ static const struct hw_3src_type {
#define E(x) BRW_ALIGN1_3SRC_EXEC_TYPE_##x
[0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
[BRW_REGISTER_TYPE_NF] = { GFX11_ALIGN1_3SRC_REG_TYPE_NF, E(FLOAT) },
[BRW_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) },
[BRW_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
@@ -402,7 +398,6 @@ unsigned
brw_reg_type_to_size(enum brw_reg_type type)
{
static const unsigned type_size[] = {
[BRW_REGISTER_TYPE_NF] = 8,
[BRW_REGISTER_TYPE_DF] = 8,
[BRW_REGISTER_TYPE_F] = 4,
[BRW_REGISTER_TYPE_HF] = 2,
@@ -435,7 +430,6 @@ const char *
brw_reg_type_to_letters(enum brw_reg_type type)
{
static const char letters[][3] = {
[BRW_REGISTER_TYPE_NF] = "NF",
[BRW_REGISTER_TYPE_DF] = "DF",
[BRW_REGISTER_TYPE_F] = "F",
[BRW_REGISTER_TYPE_HF] = "HF",
src/intel/compiler/brw_reg_type.h
-2
View File
@@ -45,7 +45,6 @@ struct intel_device_info;
*/
enum PACKED brw_reg_type {
/** Floating-point types: @{ */
BRW_REGISTER_TYPE_NF, /* >64-bit (accumulator-only) native float (gfx11+) */
BRW_REGISTER_TYPE_DF, /* 64-bit float (double float) */
BRW_REGISTER_TYPE_F, /* 32-bit float */
BRW_REGISTER_TYPE_HF, /* 16-bit float (half float) */
@@ -72,7 +71,6 @@ static inline bool
brw_reg_type_is_floating_point(enum brw_reg_type type)
{
switch (type) {
case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_F:
case BRW_REGISTER_TYPE_HF:
src/intel/compiler/brw_shader.cpp
-6
View File
@@ -74,8 +74,6 @@ fs_reg_saturate_immediate(fs_reg *reg)
unreachable("unimplemented: saturate vector immediate");
case BRW_REGISTER_TYPE_HF:
unreachable("unimplemented: saturate HF immediate");
case BRW_REGISTER_TYPE_NF:
unreachable("no NF immediates");
}
if (size < 8) {
@@ -128,8 +126,6 @@ fs_reg_negate_immediate(fs_reg *reg)
case BRW_REGISTER_TYPE_HF:
reg->ud ^= 0x80008000;
return true;
case BRW_REGISTER_TYPE_NF:
unreachable("no NF immediates");
}
return false;
@@ -175,8 +171,6 @@ fs_reg_abs_immediate(fs_reg *reg)
case BRW_REGISTER_TYPE_HF:
reg->ud &= ~0x80008000;
return true;
case BRW_REGISTER_TYPE_NF:
unreachable("no NF immediates");
}
return false;
src/intel/compiler/test_eu_validate.cpp
-2
View File
@@ -244,7 +244,6 @@ TEST_P(validation_test, invalid_type_encoding)
enum brw_reg_type type;
bool expected_result;
} test_case[] = {
{ BRW_REGISTER_TYPE_NF, devinfo.ver == 11 && file != IMM },
{ BRW_REGISTER_TYPE_DF, devinfo.has_64bit_float },
{ BRW_REGISTER_TYPE_F, true },
{ BRW_REGISTER_TYPE_HF, true },
@@ -434,7 +433,6 @@ TEST_P(validation_test, invalid_type_encoding_3src_a1)
bool expected_result;
} test_case[] = {
#define E(x) ((unsigned)BRW_ALIGN1_3SRC_EXEC_TYPE_##x)
{ BRW_REGISTER_TYPE_NF, E(FLOAT), devinfo.ver == 11 },
{ BRW_REGISTER_TYPE_DF, E(FLOAT), devinfo.has_64bit_float },
{ BRW_REGISTER_TYPE_F, E(FLOAT), true },
{ BRW_REGISTER_TYPE_HF, E(FLOAT), true },