diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index bd531e246de..65ebb006fc1 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -1229,9 +1229,6 @@ src0_3src(FILE *file, const struct intel_device_info *devinfo, } else if (brw_inst_3src_a1_src0_reg_file(devinfo, inst) == BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) { _file = BRW_GENERAL_REGISTER_FILE; - } else if (brw_inst_3src_a1_src0_type(devinfo, inst) == - BRW_REGISTER_TYPE_NF) { - _file = BRW_ARCHITECTURE_REGISTER_FILE; } else { _file = BRW_IMMEDIATE_VALUE; uint16_t imm_val = brw_inst_3src_a1_src0_imm(devinfo, inst); @@ -1587,7 +1584,6 @@ imm(FILE *file, const struct brw_isa_info *isa, enum brw_reg_type type, format(file, "/* %-gHF */", _mesa_half_to_float((uint16_t) brw_inst_imm_ud(devinfo, inst))); break; - case BRW_REGISTER_TYPE_NF: case BRW_REGISTER_TYPE_UB: case BRW_REGISTER_TYPE_B: format(file, "*** invalid immediate type %d ", type); diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c index fbfbae2f9b4..9430da745b8 100644 --- a/src/intel/compiler/brw_eu_compact.c +++ b/src/intel/compiler/brw_eu_compact.c @@ -1507,7 +1507,6 @@ compact_immediate(const struct intel_device_info *devinfo, if (((short)imm >> 11) == 0 || ((short)imm >> 11) == -1) return imm & 0xfff; break; - case BRW_REGISTER_TYPE_NF: case BRW_REGISTER_TYPE_DF: case BRW_REGISTER_TYPE_Q: case BRW_REGISTER_TYPE_UQ: @@ -1550,7 +1549,6 @@ uncompact_immediate(const struct intel_device_info *devinfo, /* Extend the 12th bit into the high 4 bits and replicate */ return ((int)(compact_imm << 20) >> 4) | ((unsigned short)((short)(compact_imm << 4) >> 4)); - case BRW_REGISTER_TYPE_NF: case BRW_REGISTER_TYPE_DF: case BRW_REGISTER_TYPE_Q: case BRW_REGISTER_TYPE_UQ: diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 64834362a88..505a12e13f5 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -607,11 +607,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, brw_inst_set_3src_a1_src0_hstride(devinfo, inst, to_3src_align1_hstride(src0.hstride)); brw_inst_set_3src_a1_src0_subreg_nr(devinfo, inst, phys_subnr(devinfo, src0)); - if (src0.type == BRW_REGISTER_TYPE_NF) { - brw_inst_set_3src_src0_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR); - } else { - brw_inst_set_3src_src0_reg_nr(devinfo, inst, phys_nr(devinfo, src0)); - } + brw_inst_set_3src_src0_reg_nr(devinfo, inst, phys_nr(devinfo, src0)); brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs); brw_inst_set_3src_src0_negate(devinfo, inst, src0.negate); } @@ -642,9 +638,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, } assert(src0.file == BRW_GENERAL_REGISTER_FILE || - src0.file == BRW_IMMEDIATE_VALUE || - (src0.file == BRW_ARCHITECTURE_REGISTER_FILE && - src0.type == BRW_REGISTER_TYPE_NF)); + src0.file == BRW_IMMEDIATE_VALUE); assert(src1.file == BRW_GENERAL_REGISTER_FILE || (src1.file == BRW_ARCHITECTURE_REGISTER_FILE && src1.nr == BRW_ARF_ACCUMULATOR)); diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index 3194ba073c1..9a6f36d8632 100644 --- a/src/intel/compiler/brw_eu_validate.c +++ b/src/intel/compiler/brw_eu_validate.c @@ -445,7 +445,6 @@ static enum brw_reg_type execution_type_for_type(enum brw_reg_type type) { switch (type) { - case BRW_REGISTER_TYPE_NF: case BRW_REGISTER_TYPE_DF: case BRW_REGISTER_TYPE_F: case BRW_REGISTER_TYPE_HF: @@ -506,10 +505,6 @@ execution_type(const struct brw_isa_info *isa, const brw_inst *inst) if (src0_exec_type == src1_exec_type) return src0_exec_type; - if (src0_exec_type == BRW_REGISTER_TYPE_NF || - src1_exec_type == BRW_REGISTER_TYPE_NF) - return BRW_REGISTER_TYPE_NF; - if (src0_exec_type == BRW_REGISTER_TYPE_Q || src1_exec_type == BRW_REGISTER_TYPE_Q) return BRW_REGISTER_TYPE_Q; diff --git a/src/intel/compiler/brw_fs_combine_constants.cpp b/src/intel/compiler/brw_fs_combine_constants.cpp index 8c5c9566950..d07680f33ce 100644 --- a/src/intel/compiler/brw_fs_combine_constants.cpp +++ b/src/intel/compiler/brw_fs_combine_constants.cpp @@ -1097,7 +1097,6 @@ add_candidate_immediate(struct table *table, fs_inst *inst, unsigned ip, switch (inst->src[i].type) { case BRW_REGISTER_TYPE_DF: - case BRW_REGISTER_TYPE_NF: case BRW_REGISTER_TYPE_F: case BRW_REGISTER_TYPE_HF: v->type = float_only; diff --git a/src/intel/compiler/brw_gram.y b/src/intel/compiler/brw_gram.y index 2a37621fbe8..ee7df440a25 100644 --- a/src/intel/compiler/brw_gram.y +++ b/src/intel/compiler/brw_gram.y @@ -366,7 +366,7 @@ add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type t %token TYPE_Q TYPE_UQ %token TYPE_V TYPE_UV %token TYPE_F TYPE_HF -%token TYPE_DF TYPE_NF +%token TYPE_DF %token TYPE_VF /* label */ @@ -1875,7 +1875,6 @@ reg_type: | TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; } | TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; } | TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; } - | TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; } ; imm_type: diff --git a/src/intel/compiler/brw_lex.l b/src/intel/compiler/brw_lex.l index 1cdfce91291..b3091292102 100644 --- a/src/intel/compiler/brw_lex.l +++ b/src/intel/compiler/brw_lex.l @@ -303,7 +303,6 @@ switch { return SWITCH; } :?DF { return TYPE_DF; } :?F { return TYPE_F; } :?HF { return TYPE_HF; } -:?NF { return TYPE_NF; } :?Q { return TYPE_Q; } :?UB { return TYPE_UB; } :?UD { return TYPE_UD; } diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h index 8e610a671c6..35c1f926b47 100644 --- a/src/intel/compiler/brw_reg.h +++ b/src/intel/compiler/brw_reg.h @@ -265,7 +265,6 @@ brw_regs_negative_equal(const struct brw_reg *a, const struct brw_reg *b) return false; case BRW_REGISTER_TYPE_UB: case BRW_REGISTER_TYPE_B: - case BRW_REGISTER_TYPE_NF: default: unreachable("not reached"); } @@ -292,7 +291,6 @@ type_sz(unsigned type) case BRW_REGISTER_TYPE_UQ: case BRW_REGISTER_TYPE_Q: case BRW_REGISTER_TYPE_DF: - case BRW_REGISTER_TYPE_NF: return 8; case BRW_REGISTER_TYPE_UD: case BRW_REGISTER_TYPE_D: diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c index c7873192574..0da6a40bfd4 100644 --- a/src/intel/compiler/brw_reg_type.c +++ b/src/intel/compiler/brw_reg_type.c @@ -52,7 +52,6 @@ enum hw_reg_type { GFX11_HW_REG_TYPE_HF = 8, GFX11_HW_REG_TYPE_F = 9, GFX11_HW_REG_TYPE_DF = 10, - GFX11_HW_REG_TYPE_NF = 11, }; enum hw_imm_type { @@ -112,7 +111,6 @@ static const struct hw_type { }, gfx11_hw_type[] = { [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID }, - [BRW_REGISTER_TYPE_NF] = { GFX11_HW_REG_TYPE_NF, INVALID }, [BRW_REGISTER_TYPE_F] = { GFX11_HW_REG_TYPE_F, GFX11_HW_IMM_TYPE_F }, [BRW_REGISTER_TYPE_HF] = { GFX11_HW_REG_TYPE_HF, GFX11_HW_IMM_TYPE_HF }, [BRW_REGISTER_TYPE_VF] = { INVALID, GFX11_HW_IMM_TYPE_VF }, @@ -180,7 +178,6 @@ enum hw_3src_reg_type { GFX10_ALIGN1_3SRC_REG_TYPE_HF = 0b000, GFX10_ALIGN1_3SRC_REG_TYPE_F = 0b001, GFX10_ALIGN1_3SRC_REG_TYPE_DF = 0b010, - GFX11_ALIGN1_3SRC_REG_TYPE_NF = 0b011, /** @} */ /** When ExecutionDatatype is 0: @{ */ @@ -208,7 +205,6 @@ static const struct hw_3src_type { #define E(x) BRW_ALIGN1_3SRC_EXEC_TYPE_##x [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID }, - [BRW_REGISTER_TYPE_NF] = { GFX11_ALIGN1_3SRC_REG_TYPE_NF, E(FLOAT) }, [BRW_REGISTER_TYPE_F] = { GFX10_ALIGN1_3SRC_REG_TYPE_F, E(FLOAT) }, [BRW_REGISTER_TYPE_HF] = { GFX10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) }, @@ -402,7 +398,6 @@ unsigned brw_reg_type_to_size(enum brw_reg_type type) { static const unsigned type_size[] = { - [BRW_REGISTER_TYPE_NF] = 8, [BRW_REGISTER_TYPE_DF] = 8, [BRW_REGISTER_TYPE_F] = 4, [BRW_REGISTER_TYPE_HF] = 2, @@ -435,7 +430,6 @@ const char * brw_reg_type_to_letters(enum brw_reg_type type) { static const char letters[][3] = { - [BRW_REGISTER_TYPE_NF] = "NF", [BRW_REGISTER_TYPE_DF] = "DF", [BRW_REGISTER_TYPE_F] = "F", [BRW_REGISTER_TYPE_HF] = "HF", diff --git a/src/intel/compiler/brw_reg_type.h b/src/intel/compiler/brw_reg_type.h index e124bc1054d..dc953344b11 100644 --- a/src/intel/compiler/brw_reg_type.h +++ b/src/intel/compiler/brw_reg_type.h @@ -45,7 +45,6 @@ struct intel_device_info; */ enum PACKED brw_reg_type { /** Floating-point types: @{ */ - BRW_REGISTER_TYPE_NF, /* >64-bit (accumulator-only) native float (gfx11+) */ BRW_REGISTER_TYPE_DF, /* 64-bit float (double float) */ BRW_REGISTER_TYPE_F, /* 32-bit float */ BRW_REGISTER_TYPE_HF, /* 16-bit float (half float) */ @@ -72,7 +71,6 @@ static inline bool brw_reg_type_is_floating_point(enum brw_reg_type type) { switch (type) { - case BRW_REGISTER_TYPE_NF: case BRW_REGISTER_TYPE_DF: case BRW_REGISTER_TYPE_F: case BRW_REGISTER_TYPE_HF: diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index fa1f5404079..00a642f954f 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -74,8 +74,6 @@ fs_reg_saturate_immediate(fs_reg *reg) unreachable("unimplemented: saturate vector immediate"); case BRW_REGISTER_TYPE_HF: unreachable("unimplemented: saturate HF immediate"); - case BRW_REGISTER_TYPE_NF: - unreachable("no NF immediates"); } if (size < 8) { @@ -128,8 +126,6 @@ fs_reg_negate_immediate(fs_reg *reg) case BRW_REGISTER_TYPE_HF: reg->ud ^= 0x80008000; return true; - case BRW_REGISTER_TYPE_NF: - unreachable("no NF immediates"); } return false; @@ -175,8 +171,6 @@ fs_reg_abs_immediate(fs_reg *reg) case BRW_REGISTER_TYPE_HF: reg->ud &= ~0x80008000; return true; - case BRW_REGISTER_TYPE_NF: - unreachable("no NF immediates"); } return false; diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp index 50de3006812..1be960af29e 100644 --- a/src/intel/compiler/test_eu_validate.cpp +++ b/src/intel/compiler/test_eu_validate.cpp @@ -244,7 +244,6 @@ TEST_P(validation_test, invalid_type_encoding) enum brw_reg_type type; bool expected_result; } test_case[] = { - { BRW_REGISTER_TYPE_NF, devinfo.ver == 11 && file != IMM }, { BRW_REGISTER_TYPE_DF, devinfo.has_64bit_float }, { BRW_REGISTER_TYPE_F, true }, { BRW_REGISTER_TYPE_HF, true }, @@ -434,7 +433,6 @@ TEST_P(validation_test, invalid_type_encoding_3src_a1) bool expected_result; } test_case[] = { #define E(x) ((unsigned)BRW_ALIGN1_3SRC_EXEC_TYPE_##x) - { BRW_REGISTER_TYPE_NF, E(FLOAT), devinfo.ver == 11 }, { BRW_REGISTER_TYPE_DF, E(FLOAT), devinfo.has_64bit_float }, { BRW_REGISTER_TYPE_F, E(FLOAT), true }, { BRW_REGISTER_TYPE_HF, E(FLOAT), true },