intel: Add intel_device_info::has_systolic

Gfx125+ has systolic, with exception for MTL and some ARL
variants.  Update code and tests to use it.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34506>
This commit is contained in:
Caio Oliveira
2025-03-28 16:39:51 -07:00
committed by Marge Bot
parent bf5273dd38
commit adfab666a4
4 changed files with 13 additions and 10 deletions
+2 -5
View File
@@ -103,11 +103,8 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
compiler->indirect_ubos_use_sampler = devinfo->ver < 12;
compiler->lower_dpas = devinfo->verx10 < 125 ||
intel_device_info_is_mtl(devinfo) ||
(intel_device_info_is_arl(devinfo) &&
devinfo->platform != INTEL_PLATFORM_ARL_H) ||
debug_get_bool_option("INTEL_LOWER_DPAS", false);
compiler->lower_dpas = !devinfo->has_systolic ||
debug_get_bool_option("INTEL_LOWER_DPAS", false);
nir_lower_int64_options int64_options =
nir_lower_imul64 |
+5 -5
View File
@@ -2984,7 +2984,7 @@ TEST_P(validation_test, add3_immediate_types)
TEST_P(validation_test, dpas_sdepth)
{
if (devinfo.verx10 < 125)
if (!devinfo.has_systolic)
return;
static const enum gfx12_systolic_depth depth[] = {
@@ -3017,7 +3017,7 @@ TEST_P(validation_test, dpas_sdepth)
TEST_P(validation_test, dpas_exec_size)
{
if (devinfo.verx10 < 125)
if (!devinfo.has_systolic)
return;
static const enum brw_execution_size test_vectors[] = {
@@ -3056,7 +3056,7 @@ TEST_P(validation_test, dpas_exec_size)
TEST_P(validation_test, dpas_sub_byte_precision)
{
if (devinfo.verx10 < 125)
if (!devinfo.has_systolic)
return;
static const struct {
@@ -3182,7 +3182,7 @@ TEST_P(validation_test, dpas_sub_byte_precision)
TEST_P(validation_test, dpas_types)
{
if (devinfo.verx10 < 125)
if (!devinfo.has_systolic)
return;
if (devinfo.ver >= 20)
@@ -3306,7 +3306,7 @@ TEST_P(validation_test, dpas_types)
TEST_P(validation_test, dpas_src_subreg_nr)
{
if (devinfo.verx10 < 125)
if (!devinfo.has_systolic)
return;
#define TV(dt, od, t0, o0, t1, o1, o2, r) \
+5
View File
@@ -1040,6 +1040,7 @@ static const struct intel_device_info intel_device_info_sg1 = {
.has_ray_tracing = true, \
.has_mesh_shading = true, \
.has_bfloat16 = true, \
.has_systolic = true, \
.has_coarse_pixel_primitive_and_cb = true, \
.needs_null_push_constant_tbimr_workaround = true, \
.simulator_id = 29
@@ -1104,6 +1105,8 @@ static const struct intel_device_info intel_device_info_atsm_g11 = {
.platform = INTEL_PLATFORM_ ## platform_suffix, \
.has_64bit_float = true, \
.has_64bit_float_via_math_pipe = true, \
/* BSpec 55414 (r53716). */ \
.has_systolic = false, \
/* BSpec 45101 (r51017) */ \
.pat = { \
/* CPU: WB, GPU: PAT 3 => WB, 1WAY */ \
@@ -1130,6 +1133,8 @@ static const struct intel_device_info intel_device_info_arl_u = {
static const struct intel_device_info intel_device_info_arl_h = {
MTL_CONFIG(ARL_H),
/* BSpec 55414 (r53716). */
.has_systolic = true,
};
#define XE2_FEATURES \
+1
View File
@@ -279,6 +279,7 @@ Struct("intel_device_info",
Member("bool", "has_64bit_int", compiler_field=True),
Member("bool", "has_bfloat16", compiler_field=True),
Member("bool", "has_integer_dword_mul", compiler_field=True),
Member("bool", "has_systolic", compiler_field=True),
Member("bool", "supports_simd16_3src", compiler_field=True),
Member("bool", "disable_ccs_repack"),