78a881af43
intel/genxml: add GAM done register description
...
Useful if you encounter some kind of pagefault (including with
AUX-TT).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27058 >
2024-01-15 11:16:40 +00:00
4868408e6e
intel/genxml: Add 3DSTATE_PS definitions needed for dual-SIMD8 dispatch on Gfx12+.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
2aea09c8de
intel/genxml: Add BCS/VD0 aux table base address register
...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26409 >
2023-12-14 00:53:15 +00:00
544c5c006c
intel/genxml: add the Gen12+ TR-TT registers
...
These are the registers we're going to use for now.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26036 >
2023-11-04 02:06:52 +00:00
6f1b1d6330
intel/genxml: Auto-import genxml files using genxml_import.py
...
$ src/intel/genxml/genxml_import.py --import
This can be reversed with:
$ src/intel/genxml/genxml_import.py --flatten
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593 >
2023-09-14 11:05:16 -07:00
3e9f366b70
genxml/gfx12: rename Tiled Resource Mode
...
To match documentation.
BSpec 46965
TGL PRMs, Volume 2d: Command Reference: Structures, 3DSTATE_HIER_DEPTH_BUFFER_BODY
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620 >
2023-09-01 23:22:17 +00:00
614efeeafe
intel/genxml: set a default value for "Pixel Position Offset Enable" in genxml
...
Set the default value for "Pixel Position Offset Enable" when emitting
3DSTATE_MULTISAMPLE in the genxml so that we can drop it from blorp
and genX_state.
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23936 >
2023-07-18 22:25:38 +00:00
8166c1f8c1
intel/genxml: Drop incorrect compute aux-inv register entry
...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23958 >
2023-07-07 18:05:47 +00:00
b4ab4e8549
intel/genxml: Add COMPCS0 aux-table registers
...
Bspec 43904 defines COMPCS0_CCS_AUX_INV to 042C8h and Bspec 43882
defines COMPCS0_AUX_TABLE_BASE_ADDR to 042C4h.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23958 >
2023-07-07 18:05:47 +00:00
6535b0c0ea
intel/genxml: Update RENDER_SURFACE_STATE Fields
...
I went through the RENDER_SURFACE_STATE docs today and found a number
of fields that are simply gone, marked as "must be zero", or had their
enum meanings change. Update those here.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23684 >
2023-06-29 21:45:14 +00:00
f592727130
intel/genxml: Add Compute/Blitter CCS aux invalidation register
...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786 >
2023-06-26 15:57:39 -07:00
b8dc7675f2
intel/genxml: changes the type for predicted weight to unsigned.
...
Turned out to be unsigned here after some experiments.
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Reviewed-by: Dave Airlie <airlied@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23790 >
2023-06-26 15:08:00 +09:00
1b3669a1ed
intel: Initialize FF_MODE2 on all Gfx12 platforms
...
On Alchemist, the FF_MODE2 documentation says that we must set the
FF_MODE2 timer values for GS and HS to 224. The hardware performance
tuning guide also recommends setting the TDS timer to 4.
On Tigerlake, i915 applies workarounds to set the GS timer to 224
(failing to do so can cause HS/DS unit hangs), and the TDS timer to 4
(for performance). It doesn't currently apply a HS timer there, and
I'm not sure if it's strictly necessary, but given that Alchemist
needed it, and the other two settings matched, let's assume that it
ought to match as well.
Unfortunately, there has been a bug in the i915 workarounds
infrastructure for non-masked context registers where writing one
field of the register zeroes out all the others. So, I believe the
Tigerlake TDS timer value of 4 isn't being applied correctly there,
though the register is also not readable on that platform which
makes it hard to verify. So, this may also speed up tessellation.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9233
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23839 >
2023-06-24 01:20:36 +00:00
d5f8265e05
intel/genxml: add a command VD_CONTROL_STATE to gen12/125
...
It's essentially needed to execute hevc decoding on gen12.
Note that we set HCP by default.
- Command OpCode : VDENC(1), HCP(7), AVP(3)
- SubOpcode : HCP(10), VDENC(11)
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202 >
2023-05-19 06:15:01 +00:00
27dcd18210
intel/genxml: align some fields on gen9/11/12/125 with media driver.
...
Most of them are length of each instruction and the rest are
some corrections on specific gens.
v1. Added a default value to DWordLength of each instruction.
( Lionel Landwerlin <lionel.g.landwerlin@intel.com > )
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202 >
2023-05-19 06:15:01 +00:00
b3a1a8c617
intel/genxml: conform some fields to each other gen.
...
There are same fields across gens but the existing xmls are not exactly same,
which needs to be fixed.
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202 >
2023-05-19 06:15:01 +00:00
44bc651aba
intel/genxml: fix num bits of some MOCS fields
...
Actually the first bit is a bit of protected mask (or reserved)
and the next 6 bits are for MOCS but they are being handled together
currently in isl_device_setup_mocs. So we need to fix some MOCS fields
defined as 6 bits to 7 bits.
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202 >
2023-05-19 06:15:01 +00:00
f85b2cbe33
anv/video: fix chroma qp to be a integer value.
...
This is just a cleanup to the genxml
Fixes: 98c58a16eflionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21433 >
2023-03-14 07:32:00 +00:00
42e8a2c1d6
genxml: fix border color offset field on Gfx12+
...
I wonder if the docs are correct for Gfx11 because this is the
generation that gave us the Bindless Sampler Heap of 4Gb. So it would
make sense that the border colors can also be placed anywhere in that
4Gb heap.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21600 >
2023-03-01 08:45:11 +00:00
bff627142d
intel/genxml: add missing power well control bits
...
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20782 >
2023-02-08 02:56:28 +00:00
cfc62802f8
intel/genxml: align some of the fields with the media driver
...
These values are taking from runtime interrogation of the media driver.
It would be nice to know if they are correct, but they work.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20782 >
2023-02-08 02:56:28 +00:00
0813c1a6fa
intel/genxml: set unused 3DSTATE_PS_EXTRA field as mbz
...
Wa_14015360517 mentions situations where HW produces invalid
occlusion query results when "Pixel Shader Does not write to RT"
bit is set.
"When Pixel Shader Kills Pixel is set, SW must perform a dummy render
target write from the shader and not set this bit, so that Occlusion
Query is correct."
Another situation is when writing to UAV or to NULL render target.
Patch sets field as 'must be zero' to discourage possible use of it.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20849 >
2023-01-24 10:28:15 +00:00
ebdf6a7926
intel/genxml: Drop CACHE_MODE_SS definition.
...
This is a global register which isn't settable by userspace contexts.
It also shouldn't appear in any of our aubinator decodes from error
states or aub dumps, as no userspace batch should be setting it.
So it's not very valuable to have here. Just makes us think we can
set it. Plus, a lot of the field definitions changed a bunch, and
would need updating.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20627 >
2023-01-12 21:48:40 +00:00
2add57d0c2
intel: Hook up RENDER_SURFACE_STATE::DecompressInL3
...
The sampler's decompressor seems to lack support for some types of
format re-interpretation. Use the more capable decompressor for these
cases. This will be needed to avoid regressing piglit's
arb_texture_view-rendering-formats in later commits.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19937 >
2022-12-14 03:05:24 +00:00
971e07361a
genxml: add gen12/12.5 CS prefetch disable bits
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20295 >
2022-12-13 19:22:02 +00:00
9859413bf4
intel/genxml: Add 3DPRIMITIVE_EXTENDED opcodes on Gen11+
...
On Gen11 and above, the 3DPRIMITIVE command takes an optional additional
three DWORDs of data as "extended parameters". These extended
parameters only exist in the packet if "Extended Parameters Present" is
set. Because our packing code doesn't handle variable-length commands
well, this commit adds a second version of the command which isn't real
but is just a copy of 3DPRIMITIVE with the additional dwords where the
"Extended Parameters Present" defaults to true and "DWord Length" is
adjusted by 3 as needed. The 3DPRIMITIVE command is then the gen4-9
version which still works fine but doesn't have the new parameters.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20295 >
2022-12-13 19:22:02 +00:00
781a16382d
intel/genxml: Make some fields Booleans
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20295 >
2022-12-13 19:22:02 +00:00
0fa540ef61
iris: Reduce use of RHWO optimization (Wa_1508744258)
...
Implement Wa_1508744258:
Disable RHWO by setting 0x7010[14] by default except during resolve
pass.
Disable the RCC RHWO optimization at all times except when resolving
single sampled color surfaces. MCS partial resolves are done via
software (i.e., not via a HW bit) and so are not expected to need this
workaround.
Reviewed-by: Mark Janes <markjanes@swizzler.org >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19360 >
2022-10-31 23:26:06 +00:00
8c8a1966ab
intel/genxml: reprocess xml with elementree output
...
This makes two relatively small changes, first it addes the encoding to
the xml delcaration, and switches the quote style. Second, it changes
the final newline. These seemed minor enough to not warrent patches to
make the old wrter do the same thing as the new writer.
Reviewed-by: Eric Engestrom <eric@engestrom.ch >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955 >
2022-10-12 10:59:06 -07:00
b876f4daa9
intel/genxml: re-process with extra whitespace removed
...
Reviewed-by: Eric Engestrom <eric@engestrom.ch >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955 >
2022-10-12 10:59:01 -07:00
9acd459bee
intel/genxml: re-process with space before />
...
Reviewed-by: Eric Engestrom <eric@engestrom.ch >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18955 >
2022-10-12 10:58:56 -07:00
3f0da1bbfa
intel/genxml: run gen_sort_tags on all of the xml
...
Reviewd-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18917 >
2022-10-01 14:03:49 -07:00
98bd984977
intel/genxml: Add XY_FAST_COLOR_BLT
...
We'll need to use this for VkCmdFillBuffer on transfer queues.
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15183 >
2022-09-28 08:41:35 +00:00
f4386b81e6
intel: fix typos found by codespell
...
Acked-by: David Heidelberg <david.heidelberg@collabora.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17191 >
2022-06-27 10:20:55 +00:00
e3defe7ae7
intel/genxml: Delete SAMPLER_MODE register definition on Gfx12+
...
While this register still exists, it's no longer a per-context register.
Instead, on Gfx12+, SAMPLER_MODE exists per dual-subslice and is
accessed as a "multicast" register, where you write control which
version is accessed by the "steering control register".
At any rate, userspace cannot write it any longer, and so there's not
much point to it existing in our genxml (which was missing most of the
fields anyway).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628 >
2022-04-11 19:17:07 +00:00
8092704705
intel/genxml: Add new "Low Quality Filter" field on Gfx12+.
...
This allows the sampler to perform faster filtering of 8-bit UNORM
textures by filtering them at a different precision. The filtering
is intended to still be OpenGL and DirectX spec compliant.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628 >
2022-04-11 19:17:07 +00:00
9a70385e2b
intel/genxml: Add SAMPLER_STATE::Allow Low Quality LOD Calculation field
...
This allows the hardware to perform a faster LOD calculation in many
simple cases.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628 >
2022-04-11 19:17:07 +00:00
88f77aa811
anv: disable preemption on 3DPRIMITIVE on gfx12
...
To workaround a push constant corruption issue.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5963
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5662
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15753 >
2022-04-06 12:51:15 +00:00
442628b702
intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation
...
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815 >
2022-02-09 10:05:10 +00:00
3e0bffbad3
intel/genxml: Add XY_BLOCK_COPY_BLT Color Depth enum values
...
Requested by Jason.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687 >
2022-01-24 23:27:25 +00:00
e9b58116ea
genxml: fix compilation with P/I defines
...
Those names are a bit too common and sometimes clash variables.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13954 >
2021-12-06 08:02:59 +00:00
2bb8aa2942
intel/genxml: capitalize decoder mode select properly
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788 >
2021-11-15 20:13:46 +00:00
2268fc1bb6
intel/genxml: fix Picure->Picture typo
...
Ilia pointed this out.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788 >
2021-11-15 20:13:46 +00:00
dc32a164c8
intel/genxml: align QM field names across gens.
...
This just picks a consistent name.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788 >
2021-11-15 20:13:46 +00:00
5d956d65b6
intel/genxml: cleanup video xml collisions.
...
When you enable video genxml, lots of warnings about redefined things
appear, just clean those up before things get started.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788 >
2021-11-15 20:13:46 +00:00
2f58a63b2f
intel/genxml: Add XY_BLOCK_COPY_BLT on Tigerlake and later.
...
This is a new blitter command introduced on Tigerlake and expanded
substantially on XeHP. XY_BLOCK_COPY_BLT is actually fast, unlike
the legacy blitter commands. iris will use this in the future, and
anv hopefully could use it for a transfer queue someday as well.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520 >
2021-10-28 14:17:32 -07:00
9163500aa1
intel/genxml: Allow MI_FLUSH_DW on the blitter
...
Pretty sure this is how you flush the blitter.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520 >
2021-10-28 14:17:32 -07:00
7b78b2fcac
intel/genxml: Assert that all MOCS fields are non-zero on Gfx7+
...
Let's try and catch performance problems before we have to do large
painful amounts of analysis to detect a missed field.
Acked-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480 >
2021-10-28 19:45:56 +00:00
956effb88a
intel/genxml: Drop "Hierarchical Depth Buffer MOCS" field
...
This is redundant with the existing "MOCS" field. We don't need both.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480 >
2021-10-28 19:45:55 +00:00
2b86cf2850
intel/genxml: Add new Primitive ID Not Required bit field to 3DSTATE_DS
...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13474 >
2021-10-26 18:22:14 +00:00
Lionel Landwerlin