AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation

Browse Source 
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
This commit is contained in:
Tapani Pälli
2022-01-31 11:48:49 +02:00
committed by Marge Bot
parent 03e1e19246
commit 442628b702
2 changed files with 2 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/genxml/gen12.xml
+1
View File
@@ -6450,6 +6450,7 @@
<instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
<field name="DWord Length" start="0" end="7" type="uint" default="4"/>
<field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/>
<field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
src/intel/genxml/gen125.xml
+1
View File
@@ -6782,6 +6782,7 @@
<instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
<field name="DWord Length" start="0" end="7" type="uint" default="4"/>
<field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/>
<field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool"/>
<field name="Untyped Data Port Cache Flush Enable" start="11" end="11" type="bool"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/>