From 442628b70244f2c9fd0ed79e0656e999ee6fffca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Mon, 31 Jan 2022 11:48:49 +0200 Subject: [PATCH] intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: mesa-stable Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/genxml/gen12.xml | 1 + src/intel/genxml/gen125.xml | 1 + 2 files changed, 2 insertions(+) diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index 08a49c33abf..c250da0c07c 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -6450,6 +6450,7 @@ + diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml index 5ed111e6e55..45aafde4c5a 100644 --- a/src/intel/genxml/gen125.xml +++ b/src/intel/genxml/gen125.xml @@ -6782,6 +6782,7 @@ +