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intel/genxml: Add Compute/Blitter CCS aux invalidation register

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Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
This commit is contained in:
Sagar Ghuge
2023-06-21 09:46:37 -07:00
parent 55d9959e67
commit f592727130
2 changed files with 9 additions and 0 deletions
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src/intel/genxml/gen12.xml
+3
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@@ -6914,6 +6914,9 @@
<field name="Blend Optimization Fix Disable Mask" start="30" end="30" type="bool" />
<field name="Color Compression Disable Mask" start="31" end="31" type="bool" />
</register>
<register name="CCS_CCS_AUX_INV" length="1" num="0x42C0">
<field name="Aux Inv" start="0" end="0" type="bool" />
</register>
<register name="CL_INVOCATION_COUNT" length="2" num="0x2338">
<field name="CL Invocation Count Report" start="0" end="63" type="uint" />
</register>
src/intel/genxml/gen125.xml
+6
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@@ -7355,6 +7355,9 @@
<field name="Destination Depth/Stencil Resource" start="498" end="498" type="bool" />
<field name="Destination Array Index" start="501" end="511" type="uint" />
</instruction>
<register name="BCS_CCS_AUX_INV" length="1" num="0x4248">
<field name="Aux Inv" start="0" end="0" type="bool" />
</register>
<register name="BCS_INSTDONE" length="1" num="0x2206c">
<field name="Ring Enable" start="0" end="0" type="bool" />
<field name="Blitter IDLE" start="1" end="1" type="bool" default="1" />
@@ -7401,6 +7404,9 @@
<field name="Blend Optimization Fix Disable Mask" start="30" end="30" type="bool" />
<field name="Color Compression Disable Mask" start="31" end="31" type="bool" />
</register>
<register name="CCS_CCS_AUX_INV" length="1" num="0x42C0">
<field name="Aux Inv" start="0" end="0" type="bool" />
</register>
<register name="CHICKEN_RASTER_1" length="1" num="0x6204">
<field name="AA Line Quality Fix" start="5" end="5" type="bool" />
<field name="AA Line Quality Fix Mask" start="21" end="21" type="bool" />