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genxml: add gen12/12.5 CS prefetch disable bits

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20295>
This commit is contained in:
Lionel Landwerlin
2022-03-17 14:24:01 +02:00
committed by Marge Bot
parent 4a3faab512
commit 971e07361a
2 changed files with 4 additions and 0 deletions
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src/intel/genxml/gen12.xml
+2
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@@ -5715,6 +5715,8 @@
<field name="Command Type" start="29" end="31" type="uint" default="3" />
</instruction>
<instruction name="MI_ARB_CHECK" bias="1" length="1">
<field name="Pre-Parser Disable" start="0" end="0" type="bool" />
<field name="Pre-Parser Disable Mask" start="8" end="8" type="bool" />
<field name="MI Command Opcode" start="23" end="28" type="uint" default="5" />
<field name="Command Type" start="29" end="31" type="uint" default="0" />
</instruction>
src/intel/genxml/gen125.xml
+2
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@@ -6058,6 +6058,8 @@
<field name="Command Type" start="29" end="31" type="uint" default="3" />
</instruction>
<instruction name="MI_ARB_CHECK" bias="1" length="1">
<field name="Pre-Parser Disable" start="0" end="0" type="bool" />
<field name="Pre-Parser Disable Mask" start="8" end="8" type="bool" />
<field name="MI Command Opcode" start="23" end="28" type="uint" default="5" />
<field name="Command Type" start="29" end="31" type="uint" default="0" />
</instruction>